ITC 1992:
Baltimore,
MD,
USA
Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992.
IEEE Computer Society 1992, ISBN 0-7803-0760-7 BibTeX
@proceedings{DBLP:conf/itc/1992,
title = {Proceedings IEEE International Test Conference 1992, Discover
the New World of Test and Design, Baltimore, Maryland, USA, September
20-24, 1992},
booktitle = {ITC},
publisher = {IEEE Computer Society},
year = {1992},
isbn = {0-7803-0760-7},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Plenary
Keynote Address
Invited Address
Session 2:
Test Generation from Switch to Multiprocessor
- Uwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus:
Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects.
21-29 BibTeX
- Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy:
A Small Test Generator for Large Designs.
30-40 BibTeX
- Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi:
Sequential Test Generation Based on Real-Value Logic.
41-48 BibTeX
- Jaushin Lee, Janak H. Patel:
An Instruction Sequence Assembling Methodology for Testing Microprocessors.
49-58 BibTeX
Session 3:
Test Architecture
Session 4:
Boundary Scan:
Device Level Applications
Session 5:
New Approaches to BIST
Session 6:
Should We Go Beyond Stuck-at Faults to Improve Quality?
Session 7:
Testing and Diagnosis of Sequential Circuits
Session 8:
Boundary Scan:
System Level Design and Application
Session 9:
New Test and Development Methods
Session 10 - Panel:
MCM Testing:
Bringing MCMs into the Mainstream
Session 11 - Panel:
The Agony of Short Time to Market
Session 12 - Panel:
Does Object-Oriented Programming Fit in Real World ATE?
Session 13 - Panel:
Memory Testing Technology in a Gigabit Age in Japan
Session 14:
IC Manufacturer Practical Quality Improvement Techniques
Session 15:
Scan Design:
More Bang for Less Bucks
Session 16:
Analog to Digital Converter Testing
Session 17:
Board Test
Session 18:
Three Approaches to Increase Good Product Shipped
Session 19:
Boundary Scan:
Board Level Design and Analysis
Session 20:
Error Modeling and Design for Test in Mixed Signal Devices
Session 21:
ATE Timing Subsystems
Session 22:
Test Data Management
Session 23:
Bridging and Other Faults in CMOS Circuits
Session 24:
BIST Design Techniques
Session 25:
ATE Timing Accuracy and Calibration
Session 26 - Panel:
Systems Testing - The Home for All Product Test Planning?
Session 27 - Panel:
Is IC Burn-In or Burned-Out - Part 2
Session 28 - Panel:
Software Testing:
Opportunity and Nightmare
Session 29 - Panel:
P1149.4 Mixed-Signal Test Bus Framework Proposals
Session 30:
System Issues in Delay Testing
- Bejoy G. Oomman, Prasad Kongara, Chittaranjan Mallipeddi:
Amdahl Corporation Board Delay Test System.
558-567 BibTeX
- Yaron Aizenbud, Paul Chang, Moshe Leibowitz, Dave Smith, Bernd Könemann, Vijay S. Iyengar, Barry K. Rosen:
AC Test Quality: Beyond Transition Fault Coverage.
568-577 BibTeX
- Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams:
Delay Test: The Next Frontier for LSSD Test Systems.
578-587 BibTeX
- Weiwei Mao, Michael D. Ciletti:
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults.
588-597 BibTeX
Session 31:
Memory Design and Test Techniques
- Michael Nicolaidis:
Transparent BIST for RAMs.
598-607 BibTeX
- H. Maeno, K. Nii, S. Sakayanagi, S. Kato:
LSSD Compatible and Concurrently Testable Ram.
608-614 BibTeX
- Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikishi, Katsunori Suma, Kazuyasu Fujishima:
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter.
615-622 BibTeX
- Tom Chen, Glen Sunada:
A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories.
623-631 BibTeX
Session 32:
Advances in Design for Testability Techniques
Session 33:
Microprocessor Testing Case Studies
- Paul Astrachan, Todd Brooks, Jody Everett, Wai-On Law, Kenneth McIntyre, Chuong Nguyen, Charles Weng:
Testing a DSP-Based Mixed-Signal Telecommunications Chip.
669-677 BibTeX
- J. Preißner, G.-H. Huaman-Bollo, G. Mahlich, Johannes Schuck, Hans Sahm, P. Weingart, D. Weinsziehr, J. Yeandel, R. Evans:
An Open Modular Test Concept for the DSP KISS-16Vs.
678-683 BibTeX
- A. J. van de Goor, Th. J. W. Verhallen:
Functional Testing of Current Microprocessors (applied to the Intel i860TM).
684-695 BibTeX
- Marcus Rimén, Joakim Ohlsson:
A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection.
696-704 BibTeX
Session 34:
Advanced Delay Testing
Session 35: Test Synthesis
Session 36: CAE for Defect Detection and I-DDQ Testing
Session 37:
Special Topics in Mixed Signal Testing
Session 38:
Test Generation Techniques
Session 39:
Contactless Probing
Session 40:
Developments in CAD to Test
Session 41:
Unique Design,
Fault,
and Defect Issues
Session 42:
Testing Computer Software
Session 43:
High Performance Probing
Session 44:
Self-Checking,
Concurrent Testing,
and Self-repair
Session 45:
System Testing
1991 Best Paper Award
Copyright © Sat May 16 23:26:41 2009
by Michael Ley (ley@uni-trier.de)
