10. DDECS 2007:
Kraków,
Poland
Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino (Eds.):
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007.
IEEE Computer Society 2007, ISBN 1-4244-1161-0 BibTeX
Invited Presentations
Session I:
Design for Test & Defect Analysis
Session II:
SOC Design & Test
Session III:
Fault Analysis & Circuit Reliability
- Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy:
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance.
69-74 BibTeX
- Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli:
Architecture for Highly Reliable Embedded Flash Memories.
75-80 BibTeX
- Zhicheng Liang, Makoto Ikeda, Kunihiro Asada:
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology.
81-86 BibTeX
- Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams:
Accurately Determining Bridging Defects from Layout.
87-90 BibTeX
Session IV:
FPGA-Based Design
Poster Session I
- Dongsoo Kim, Gunhee Han:
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling.
113-116 BibTeX
- Valeria Sipala, Domenico Lo Presti, Nunzio Randazzo, Luigi Caponetto:
A PMT Interface for the Optical Module Front-end of a Neutrino Underwater Telescope.
117-120 BibTeX
- Santiago De Pablo, Santiago Cáceres, Jesús A. Cebrián, Manuel Berrocal:
A Proposal for ASM++ Diagrams.
121-124 BibTeX
- Piotr Buciak, Jakub Botwicz:
Lightweight Multi-threaded Network Processor Core in FPGA.
125-130 BibTeX
- Jim Torresen, Thor Arne Lovland:
Parts Obsolescence Challenges for the Electronics Industry.
131-134 BibTeX
- Khalil Arshak, Francis Adepoju, Essa Jafer:
Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application.
135-138 BibTeX
- Ireneusz Brzozowski, Andrzej Kos:
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation.
139-144 BibTeX
- Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories.
145-148 BibTeX
- Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka:
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.
149-152 BibTeX
- Daniel Tille, Görschwin Fey, Rolf Drechsler:
Instance Generation for SAT-based ATPG.
153-156 BibTeX
- Khalil Arshak, Essa Jafer, Christian Ibala:
Power Testing of an FPGA-based System Using Modelsim Code Coverage Capability.
157-160 BibTeX
- Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier:
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects.
161-164 BibTeX
Session V:
Memory Testing
Session VI:
Logic Design
Poster Session II
- Costin Cepisca, Sorin Dan Grigorescu, Mircea Covrig, Horia Andrei:
About the Efficiency of Real Time Sequences FFT Computing.
211-214 BibTeX
- Martin Simlastík, Viera Stopjaková, Libor Majer, Peter Malík:
Clockless Implementation of LEON2 for Low-Power Applications.
215-218 BibTeX
- Edward Hrynkiewicz, Stefan Kolodzinski:
Decomposition of Logic Functions in Reed-Muller Spectral Domain.
219-222 BibTeX
- Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo:
Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor.
223-226 BibTeX
- Jim Torresen, Jorgen Norendal, Kyrre Glette:
Establishing a New Course in Reconfigurable Logic System Design.
227-230 BibTeX
- Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Power Dissipation in Basic Global Clock Distribution Networks.
231-234 BibTeX
- Roman Bazylevych, Ihor Podolskyy, Lubov Bazylevych:
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters.
235-238 BibTeX
- Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Mixed Approach for Unified Logic Diagnosis.
239-242 BibTeX
- Lukás Sekanina:
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates.
243-246 BibTeX
- Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi:
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.
247-250 BibTeX
- Sergei B. Musin, Alexander A. Ivaniuk, Vyacheslav N. Yarmolik:
Multiple Errors Detection Technique for RAM.
251-254 BibTeX
- Tomasz Rudnicki, Andrzej Hlawiczka:
Test Pattern Generator for Delay Faults.
255-258 BibTeX
Session VII:
Fault Tolerance I
Session VIII:
Analog & RF Design
Session IX:
Fault Tolerance II
- Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.
295-300 BibTeX
- Manuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, José M. Ferreira:
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs.
301-306 BibTeX
- René Kothe, Heinrich Theodor Vierhaus:
Flip-Flops and Scan-Path Elements for Nanoelectronics.
307-312 BibTeX
- Pawel Pawlowski, Adam Dabrowski, Mario Schölzel:
Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic.
313-318 BibTeX
Poster Session III
- Pawel Russek, Kazimierz Wiatr:
Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing Environment.
321-324 BibTeX
- András Timár, Márta Rencz:
Design Issues of a Low Frequency Low-Pass Filter for Medical Applications Using CMOS Technology.
325-328 BibTeX
- Vladimir Havel, Karel K. Vlcek:
Feasibility of Image Compression in FPGA-based Neural Networks.
329-332 BibTeX
- Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
IP Integration Overhead Analysis in System-on-Chip Video Encoder.
333-336 BibTeX
- Ábel Vámos:
Quadrature-Phase Topology of a High Frequency Ring Oscillator.
337-340 BibTeX
- Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu:
Reticle Exposure Plans for Multi-Project Wafers.
341-344 BibTeX
- Gyula Bakonyi-Kiss, Zoltán Szucs:
Low Cost, Low Power, Intelligent Brake Temperature Sensor System for Automotive Applications.
345-348 BibTeX
- Matthias Bucher, Antonios Bazigos, Wladyslaw Grabinski:
Determining MOSFET Parameters in Moderate Inversion.
349-352 BibTeX
- Tomasz Golonek, Damian Grzechca, Jerzy Rutkowski:
Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization.
353-356 BibTeX
- Pavel Kubalík, Jirí Kvasnicka, Hana Kubatova:
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System.
357-360 BibTeX
- Jan Korenek, Petr Kobierský:
Intrusion Detection System Intended for Multigigabit Networks.
361-364 BibTeX
- Wlodzimierz Jonca:
Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit.
365-368 BibTeX
Session X:
Test Quality & Test Generation
Session XI:
Model Checking & Debugging
Session XII:
Analog & MEMS testing
Copyright © Sat May 16 23:06:18 2009
by Michael Ley (ley@uni-trier.de)
