VTS 2005:
Palm Springs,
CA,
USA
23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA.
IEEE Computer Society 2005, ISBN 0-7695-2314-5 BibTeX
Introduction
Plenary Session
1A:
Memory BIST
1B:
Delay Testing I
- Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee:
Transition Tests for High Performance Microprocessors.
29-34
Electronic Edition (link) BibTeX
- Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak:
On Silicon-Based Speed Path Identification.
35-41
Electronic Edition (link) BibTeX
- Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic:
At-Speed Transition Fault Testing With Low Speed Scan Enable.
42-47
Electronic Edition (link) BibTeX
1C:
IP Session - Multisite Testing
2A:
Memory Testing I
2B:
High-Speed Testing and Clock Skew Compensation
- Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt:
Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities.
75-84
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- Hitoshi Iwai, Atsushi Nakayama, Naoko Itoga, Kotaro Omata:
Cantilever Type Probe Card for At-Speed Memory Test on Wafer.
85-89
Electronic Edition (link) BibTeX
- Martin Omaña, Daniele Rossi, Cecilia Metra:
Low Cost Scheme for On-Line Clock Skew Compensation.
90-95
Electronic Edition (link) BibTeX
2C:
IP Session - DFT for SoCs in Wireless Applications
3A:
Test Data Compression and Self-Test
- Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel:
Implementing a Scheme for External Deterministic Self-Test.
101-106
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- Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen:
On A Software-Based Self-Test Methodology and Its Application.
107-113
Electronic Edition (link) BibTeX
- Janusz Rajski, Jerzy Tyszer:
Synthesis of X-Tolerant Convolutional Compactors.
114-119
Electronic Edition (link) BibTeX
3B:
Analog Testing I
3C:
IP Session - Soft Errors
4A:
Defect-Oriented Testing
4B:
IP Session - Adaptive Test
4C:
IP Session - High Speed I/O Test
5A:
Panel Session - Robust Design from Unreliable Components:
Why? When? How?
5B:
Emerging Technologies - Reliable and Fault-Tolerant Wireless Sensor Networks
6A:
Memory Testing II
- Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg:
A New Algorithm for Dynamic Faults Detection in RAMs.
177-182
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- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan:
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.
183-188
Electronic Edition (link) BibTeX
- John C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott:
Test and Characterization of a Variable-Capacity Multilevel DRAM.
189-197
Electronic Edition (link) BibTeX
6B:
FPGA & MEMS Testing
6C:
IP Session - IP in Wireless Testing
7A:
Delay Testing II
- Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press:
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.
223-228
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- Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng:
Pseudo-Functional Scan-based BIST for Delay Fault.
229-234
Electronic Edition (link) BibTeX
- Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker:
Static Compaction of Delay Tests Considering Power Supply Noise.
235-240
Electronic Edition (link) BibTeX
7B:
RF Testing
7C:
IP Session:
Embedded Memory Test & Repair Drives Higher Yield in Nanometer Technologies
8A:
Low-Power Testing
8B:
Nanometer and Circuit-Level Effects
8C:
IP Session - Test Resource Partitioning in Action
9A:
Embedded Tutorial:
Test with Variations - How Much Can Be Solved in the Design Process?
9C:
Panel Session - Are DFT and Manufacturing Test Good Boosts for DFM?
10A:
Reliability
10B:
Testing of Bridging Faults and Test Scheduling
- Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee:
Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor.
337-342
Electronic Edition (link) BibTeX
- Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker:
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
343-348
Electronic Edition (link) BibTeX
- Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota:
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.
349-354
Electronic Edition (link) BibTeX
10C:
IP Session - SoC Test Practices in Japan
11A:
Diagnosis
11B:
Analog Testing II
11C:
IP Session - Delay Fault Testing:
Industrial Case Studies
12A:
Design-for-Testability
12B:
I_DDQ Testing and Power Supply Noise Analysis
12C:
IP Session - On the Way from DFT to DFM...Looking for Systematic Marginalities
13A:
Panel Session - IEEE 1500:
Embedded Core-Based Test Standard:
Why Should I Adopt It?
13B:
Hot Topic Session - Test and DFM:
Managing Yield at 90nm and below
13C:
Panel Session - Analog TRP:
Is Convergence on Horizon?
Copyright © Sat May 16 23:47:01 2009
by Michael Ley (ley@uni-trier.de)
