ICCAD 1990:
Santa Clara,
California,
USA
IEEE/ACM International Conference on Computer-Aided Design,
ICCAD-90,
November 11-15,
1990,
Santa Clara,
CA,
USA,
Digest of Technical Papers. IEEE Computer Society,
1990,
ISBN 0-8186-2055-2
Session 1A:
Routing Algorithms and Complexity 1
Session 1B:
Timing Analysis and Verification
Session 1C:
Verification
Session 2A:
Routing Methods
Session 2B:
Performance Enhancements for Logic and Switch-Level Simulation
Session 2C:
Interacting Sequential Machines and Boolean Function Manipulation
Session 3A:
Floorplanning Algorithms
Session 3B:
Yield Maximization
Session 3C:
Sequential Verification
- Olivier Coudert, Jean Christophe Madre:
A Unified Framework for the Formal Verification of Sequential Circuits.
126-129 BibTeX
- Hervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Implicit State Enumeration of Finite State Machines Using BDDs.
130-133 BibTeX
- Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi:
ATPG Aspects of FSM Verification.
134-137 BibTeX
Session 4A:
Floorplanning Systems
Session 4B:
Circuit Simulation
Session 4C:
Logic Synthesis
Session 5A:
Analog Layout
Session 5B:
High-Level Synthesis
Session 5C:
Automatic Test Pattern Generation
Session 6A:
Layout Desgin and Verification
Session 6B:
Scheduling and Allocation
Session 6C:
Topics in Testing
Session 7A:
Analog Design and Test
Session 7B:
Datapath Synthesis
Session 7C:
Partial Scan and Test Minimization
Session 8A:
Placement
Session 8B:
Design Management in CAD Frameworks
Session 8C:
Built-In Self Test and Diagnostics
Session 9A:
Technology Driven Routing
Session 9B:
Reliability Simulation
Session 9C:
Sequential Optimization
Session 10A:
Routing Algorithms and Complexity 2
Session 10B:
Parallel Matrix Techniques
Session 10C:
Synthesis for Test and Diagnosis
- Michael J. Bryan, Srinivas Devadas, Kurt Keutzer:
Testability-Preserving Circuit Transformations.
456-459 BibTeX
- Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng:
Timing Optimization with Testability Considerations.
460-463 BibTeX
- Heh-Tyan Liaw, Jia-Horng Tsaih, Chen-Shang Lin:
Efficient Automatic Diagnosis of Digital Circuits.
464-467 BibTeX
- Masahiro Tomita, Hong-Hai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi:
An Algorithm for Locating Logic Design Errors.
468-471 BibTeX
Session 11A:
Exploratory Initiatives in CAD Frameworks
Session 11B:
Switch and Logic Simulation
Session 11C:
Combinatorial Optimization
Session 12A:
Partitioning and Module Generation
Session 12B:
Linear Circuit Simulation
Session 12C:
Synthesis Systems
- Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun:
check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits.
552-555 BibTeX
- Kaname Kuroki, Nobuyoshi Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi:
A Framework Environment for Logic Design Support System.
556-559 BibTeX
- Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs.
560-563 BibTeX
- Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura:
Multi-Level Optimization for Large Scale ASICS.
564-567 BibTeX
Copyright © Sat May 16 23:16:30 2009
by Michael Ley (ley@uni-trier.de)
