14. PATMOS 2004:
Santorini,
Greece
Enrico Macii, Odysseas G. Koufopavlou, Vassilis Paliouras (Eds.):
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings.
Lecture Notes in Computer Science 3254 Springer 2004, ISBN 3-540-23095-5 BibTeX
@proceedings{DBLP:conf/patmos/2004,
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Integrated Circuit and System Design, Power and Timing Modeling,
Optimization and Simulation; 14th International Workshop, PATMOS
2004, Santorini, Greece, September 15-17, 2004, Proceedings},
booktitle = {PATMOS},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {3254},
year = {2004},
isbn = {3-540-23095-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Speech
Invited Talks
Embedded Tutorials
Buses and Communication
Circuits and Devices (I)
- Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Performance Metric Based Optimization Protocol.
100-109
Electronic Edition (link) BibTeX
- B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Temperature Dependence in Low Power CMOS UDSM Process.
110-118
Electronic Edition (link) BibTeX
- Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti:
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.
119-128
Electronic Edition (link) BibTeX
- Nicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani:
High Yield Standard Cell Libraries: Optimization and Modeling.
129-137
Electronic Edition (link) BibTeX
- Gabriella Trucco, Giorgio Boselli, Valentino Liberali:
A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.
138-147
Electronic Edition (link) BibTeX
Low Power (I)
- Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger:
Sleepy Stack Reduction of Leakage Power.
148-158
Electronic Edition (link) BibTeX
- Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae:
A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.
159-168
Electronic Edition (link) BibTeX
- Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine:
Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.
169-178
Electronic Edition (link) BibTeX
- André K. Nieuwland, Atul Katoch, Maurice Meijer:
Reducing Cross-Talk Induced Power Consumption and Delay.
179-188
Electronic Edition (link) BibTeX
- Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre:
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.
189-197
Electronic Edition (link) BibTeX
- Geoff Merrett, Bashir M. Al-Hashimi:
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.
198-207
Electronic Edition (link) BibTeX
Architectures
- Jie Ruan, Mark G. Arnold:
Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS.
208-217
Electronic Edition (link) BibTeX
- Armin Wellig, Julien Zory, Norbert Wehn:
Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications.
218-227
Electronic Edition (link) BibTeX
- Matthias Müller, Andreas Wortmann, Dominik Mader, Sven Simon:
Register Isolation for Synthesizable Register Files.
228-237
Electronic Edition (link) BibTeX
- Carlo Brandolese, William Fornaciari, Fabio Salice:
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures.
238-247
Electronic Edition (link) BibTeX
- Giorgos Dimitrakopoulos, P. Kolovos, P. Kalogerakis, Dimitris Nikolos:
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.
248-257
Electronic Edition (link) BibTeX
Asynchronous Circuits
System Design
- Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck:
L0 Cluster Synthesis and Operation Shuffling.
311-321
Electronic Edition (link) BibTeX
- Anders Brødløs Olsen, Finn Büttner, Peter Koch:
On Combined DVS and Processor Evaluation.
322-331
Electronic Edition (link) BibTeX
- Christos Drosos, Labros Bisdounis, Dimitris Metafas, Spyros Blionas, Anna Tatsaki:
A Multi-level Validation Methodology for Wireless Network Applications.
332-341
Electronic Edition (link) BibTeX
- Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin:
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.
342-351
Electronic Edition (link) BibTeX
- Emanuele Lattanzi, Andrea Acquaviva, Alessandro Bogliolo:
Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards.
352-361
Electronic Edition (link) BibTeX
- Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Raimundo S. Barreto, Fernando F. Carvalho:
Towards a Software Power Cost Analysis Framework Using Colored Petri Net.
362-371
Electronic Edition (link) BibTeX
Circuits and Devices (II)
- Francesco Pessolano, R. I. M. P. Meijer:
A 260ps Quasi-static ALU in 90nm CMOS.
372-380
Electronic Edition (link) BibTeX
- Jean Michel Daga, Caroline Papaix, Marylene Combe, Emmanuel Racape, Vincent Sialelli:
Embedded EEPROM Speed Optimization Using System Power Supply Resources.
381-391
Electronic Edition (link) BibTeX
- Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.
392-401
Electronic Edition (link) BibTeX
- Uri Frank, Ran Ginosar:
A Predictive Synchronizer for Periodic Clock Domains.
402-412
Electronic Edition (link) BibTeX
- Jürgen Fischer, Ettore Amirante, Agnese Bargagli-Stoffi, Philip Teichmann, Dominik Gruber, Doris Schmitt-Landsiedel:
Power Supply Net for Adiabatic Circuits.
413-422
Electronic Edition (link) BibTeX
Interconnect and Physical Design
- Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada:
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.
423-432
Electronic Edition (link) BibTeX
- Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
433-441
Electronic Edition (link) BibTeX
- Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan:
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.
442-452
Electronic Edition (link) BibTeX
- Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke:
Wirelength Reduction Using 3-D Physical Design.
453-462
Electronic Edition (link) BibTeX
- Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
On Skin Effect in On-Chip Interconnects.
463-470
Electronic Edition (link) BibTeX
Security and Safety
- Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev:
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.
471-480
Electronic Edition (link) BibTeX
- Marco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti:
A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.
481-490
Electronic Edition (link) BibTeX
- Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger:
A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design.
491-500
Electronic Edition (link) BibTeX
- Athanasios Kakarountas, Vassilis Spiliotopoulos, Spiridon Nikolaidis, Constantinos E. Goutis:
The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems.
501-509
Electronic Edition (link) BibTeX
Low Power (II)
- David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems.
510-520
Electronic Edition (link) BibTeX
- Gianluca Palermo, Cristina Silvano:
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures.
521-531
Electronic Edition (link) BibTeX
- Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat:
Power Consumption of Performance-Scaled SIMD Processors.
532-540
Electronic Edition (link) BibTeX
- Andrea Bona, Vittorio Zaccaria, Roberto Zafalon:
Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.
541-552
Electronic Edition (link) BibTeX
- Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu:
Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling.
553-563
Electronic Edition (link) BibTeX
Low-Power Processing (Poster)
- Ana Rusu, Alexei Borodenkov, Mohammed Ismail, Hannu Tenhunen:
Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers.
564-573
Electronic Edition (link) BibTeX
- Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo:
Power Aware Dividers in FPGA.
574-584
Electronic Edition (link) BibTeX
- Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan:
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses.
585-592
Electronic Edition (link) BibTeX
- Nikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis:
The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms.
593-602
Electronic Edition (link) BibTeX
- Patricia Guitton-Ouhamou, Hanene Ben Fradj, Cécile Belleudy, Spiridon Nikolaidis:
Low Power Co-design Tool and Power Optimization of Schedules and Memory System.
603-612
Electronic Edition (link) BibTeX
- Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis:
Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.
613-622
Electronic Edition (link) BibTeX
- Sonia López, Oscar Garnica, José Manuel Colmenar:
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.
623-632
Electronic Edition (link) BibTeX
- Nikolaos Kavvadias, Spiridon Nikolaidis:
Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors.
633-642
Electronic Edition (link) BibTeX
- Amjad Mohsen, Richard Hofmann:
Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems.
643-651
Electronic Edition (link) BibTeX
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.
652-661
Electronic Edition (link) BibTeX
- Kenny Johansson, Oscar Gustafsson, Lars Wanhammar:
Power Estimation for Ripple-Carry Adders with Correlated Input Data.
662-674
Electronic Edition (link) BibTeX
- Mark G. Arnold:
LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS.
675-684
Electronic Edition (link) BibTeX
Digital Design (Poster)
- Leonardo Valencia:
Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits.
685-690
Electronic Edition (link) BibTeX
- Myeong-Hoon Oh, Dong-Soo Har:
A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic.
691-700
Electronic Edition (link) BibTeX
- Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun:
Pipelines in Dynamic Dual-Rail Circuits.
701-710
Electronic Edition (link) BibTeX
- Ali Manzak, Chaitali Chakrabarti:
Optimum Buffer Size for Dynamic Voltage Processors.
711-721
Electronic Edition (link) BibTeX
- A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne:
Design Optimization with Automated Cell Generation.
722-731
Electronic Edition (link) BibTeX
- Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis:
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.
732-741
Electronic Edition (link) BibTeX
- Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis:
A Novel Constant-Time Fault-Secure Binary Counter.
742-749
Electronic Edition (link) BibTeX
- Dimitrios Velenis, Eby G. Friedman:
Buffer Sizing for Crosstalk Induced Delay Uncertainty.
750-759
Electronic Edition (link) BibTeX
- Panagiotis D. Vouzis, Vassilis Paliouras:
Optimal Logarithmic Representation in Terms of SNR Behavior.
760-769
Electronic Edition (link) BibTeX
- Y. S. Son, J. W. Na:
A New Logic Transformation Method for Both Low Power and High Testability.
770-779
Electronic Edition (link) BibTeX
- Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow:
Energy-Efficient Hardware Architecture for Variable N-point 1D DCT.
780-788
Electronic Edition (link) BibTeX
Modeling and Simulation (Poster)
- Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.
789-798
Electronic Edition (link) BibTeX
- Alexander Maili, Damian Dalton, Christian Steger:
A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.
799-808
Electronic Edition (link) BibTeX
- Howard Chen, Daniel L. Ostapko:
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis.
809-818
Electronic Edition (link) BibTeX
- Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner:
On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.
819-828
Electronic Edition (link) BibTeX
- Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa:
Signal Sampling Based Transition Modeling for Digital Gates Characterization.
829-837
Electronic Edition (link) BibTeX
- B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Physical Extension of the Logical Effort Model.
838-848
Electronic Edition (link) BibTeX
- Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Andersson, Atila Alvandpour, Christer Svensson:
An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.
849-858
Electronic Edition (link) BibTeX
- Alberto García Ortiz, Tudor Murgan, Manfred Glesner:
Moment-Based Estimation of Switching Activity for Correlated Distributions.
859-868
Electronic Edition (link) BibTeX
- Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson:
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects.
869-878
Electronic Edition (link) BibTeX
- Tobias Gemmeke, Tobias G. Noll:
A Physically Oriented Model to Quantify the Noise-on-Delay Effect.
879-888
Electronic Edition (link) BibTeX
- Stefan Cserveny, Jean-Marc Masgonty, Christian Piguet:
Noise Margin in Low Power SRAM Cells.
889-898
Electronic Edition (link) BibTeX
- Peter Celinski, Derek Abbott, Sorin Cotofana:
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.
899-906
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:32:38 2009
by Michael Ley (ley@uni-trier.de)