| 2006 |
|---|
| 6 | EE | Vidyasagar Nookala,
David J. Lilja,
Sachin S. Sapatnekar:
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.
ISLPED 2006: 298-303 |
| 5 | EE | Vidyasagar Nookala,
Ying Chen,
David J. Lilja,
Sachin S. Sapatnekar:
Comparing simulation techniques for microarchitecture-aware floorplanning.
ISPASS 2006: 80-88 |
| 2005 |
|---|
| 4 | EE | Jaskirat Singh,
Vidyasagar Nookala,
Zhi-Quan Luo,
Sachin S. Sapatnekar:
Robust gate sizing by geometric programming.
DAC 2005: 315-320 |
| 3 | EE | Vidyasagar Nookala,
Ying Chen,
David J. Lilja,
Sachin S. Sapatnekar:
Microarchitecture-aware floorplanning using a statistical design of experiments approach.
DAC 2005: 579-584 |
| 2 | EE | Vidyasagar Nookala,
Sachin S. Sapatnekar:
Designing optimized pipelined global interconnects: algorithms and methodology impact.
ISCAS (1) 2005: 608-611 |
| 2004 |
|---|
| 1 | EE | Vidyasagar Nookala,
Sachin S. Sapatnekar:
A method for correcting the functionality of a wire-pipelined circuit.
DAC 2004: 570-575 |
