ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 7

Volume 7, Number 1, January 2002

• Amit Chowdhary, John P. Hayes:
  General technology mapping for field-programmable gate arrays based on lookup tables. 1-32
  Electronic Edition (ACM DL) BibTeX
• Maria K. Michael, Spyros Tragoudas:
  ATPG tools for delay faults at the functional level. 33-57
  Electronic Edition (ACM DL) BibTeX
• Roman L. Lysecky, Frank Vahid:
  Prefetching for improved bus wrapper performance in cores. 58-90
  Electronic Edition (ACM DL) BibTeX
• Shantanu Dutt, Wenyong Deng:
  Cluster-aware iterative improvement techniques for partitioning large VLSI circuits. 91-121
  Electronic Edition (ACM DL) BibTeX
• Laurence Goodby, Alex Orailoglu, Paul M. Chau:
  Microarchitectural synthesis of performance-constrained, low-power VLSI designs. 122-136
  Electronic Edition (ACM DL) BibTeX
• Luís Guerra e Silva, João P. Marques Silva, Luis Miguel Silveira, Karem A. Sakallah:
  Satisfiability models and algorithms for circuit delay computation. 137-158
  Electronic Edition (ACM DL) BibTeX
• Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien:
  Constructing and exploiting linear schedules with prescribed parallelism. 159-172
  Electronic Edition (ACM DL) BibTeX
• Ashok Jagannathan, Sung-Woo Hur, John Lillis:
  A fast algorithm for context-aware buffer insertion. 173-188
  Electronic Edition (ACM DL) BibTeX
• Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy:
  An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. 189-216
  Electronic Edition (ACM DL) BibTeX
• Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai:
  Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. 217-230
  Electronic Edition (ACM DL) BibTeX

Volume 7, Number 2, April 2002

• Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya:
  Monotone bipartitioning problem in a planar point set with applications to VLSI. 231-248
  Electronic Edition (ACM DL) BibTeX
• Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero:
  Initializability analysis of synchronous sequential circuits. 249-264
  Electronic Edition (ACM DL) BibTeX
• Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu:
  Logic transformation for low-power synthesis. 265-283
  Electronic Edition (ACM DL) BibTeX
• Russell Tessier:
  Fast placement approaches for FPGAs. 284-305
  Electronic Edition (ACM DL) BibTeX
• Min Zhao, Sachin S. Sapatnekar:
  Technology mapping algorithms for domino logic. 306-335
  Electronic Edition (ACM DL) BibTeX
• Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra:
  Global array reference allocation. 336-357
  Electronic Edition (ACM DL) BibTeX

Volume 7, Number 3, July 2002

• Chung-Wen Albert Tsao, Cheng-Kok Koh:
  UST/DME: a clock tree router for general skew constraints. 359-379
  Electronic Edition (ACM DL) BibTeX
• Apostolos A. Kountouris, Christophe Wolinski:
  Efficient scheduling of conditional behaviors for high-level synthesis. 380-412
  Electronic Edition (ACM DL) BibTeX
• Frank Vahid:
  Partitioning sequential programs for CAD using a three-step approach. 413-429
  Electronic Edition (ACM DL) BibTeX
• Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana:
  Cluster assignment for high-performance embedded VLIW processors. 430-454
  Electronic Edition (ACM DL) BibTeX
• Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj:
  Estimation of state line statistics in sequential circuits. 455-473
  Electronic Edition (ACM DL) BibTeX
• Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov:
  False-noise analysis using logic implications. 474-498
  Electronic Edition (ACM DL) BibTeX

Volume 7, Number 4, October 2002

• Majid Sarrafzadeh, Rajeev Jayaraman:
  Guest editorial. 499-500
  Electronic Edition (ACM DL) BibTeX
• Navin Vemuri, Priyank Kalla, Russell Tessier:
  BDD-based logic synthesis for LUT-based FPGAs. 501-525
  Electronic Edition (ACM DL) BibTeX
• Hongbing Fan, Jiping Liu, Yu-Liang Wu, C. K. Wong:
  Reduction design for generic universal switch blocks. 526-546
  Electronic Edition (ACM DL) BibTeX
• Andreas Dandalis, Viktor K. Prasanna:
  Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. 547-562
  Electronic Edition (ACM DL) BibTeX
• Haibo Wang, Sarma B. K. Vrudhula:
  Behavioral synthesis of field programmable analog array circuits. 563-604
  Electronic Edition (ACM DL) BibTeX
• Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh:
  Instruction generation for hybrid reconfigurable systems. 605-627
  Electronic Edition (ACM DL) BibTeX
• Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
  Performance-driven placement for dynamically reconfigurable FPGAs. 628-642
  Electronic Edition (ACM DL) BibTeX
• Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska:
  Efficient circuit clustering for area and power reduction in FPGAs. 643-663
  Electronic Edition (ACM DL) BibTeX
• Shantanu Dutt, Vinay Verma, Hasan Arslan:
  A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. 664-693
  Electronic Edition (ACM DL) BibTeX