| 2009 |
|---|
| 5 | EE | Leomar S. da Rosa Jr.,
Felipe Ribeiro Schneider,
Renato P. Ribas,
André Inácio Reis:
Switch level optimization of digital CMOS gate networks.
ISQED 2009: 324-329 |
| 2007 |
|---|
| 4 | EE | Leomar S. da Rosa Jr.,
André Inácio Reis,
Renato P. Ribas,
Felipe de Souza Marques,
Felipe Ribeiro Schneider:
A comparative study of CMOS gates with minimum transistor stacks.
SBCCI 2007: 93-98 |
| 2005 |
|---|
| 3 | EE | Felipe Ribeiro Schneider,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
Exact lower bound for the number of switches in series to implement a combinational logic cell.
ICCD 2005: 357-362 |
| 2003 |
|---|
| 2 | EE | Renato E. B. Poli,
Felipe Ribeiro Schneider,
Renato P. Ribas,
André Inácio Reis:
Unified Theory to Build Cell-Level Transistor Networks from BDDs.
SBCCI 2003: 199-204 |
| 2002 |
|---|
| 1 | | Felipe Ribeiro Schneider,
Vinícius P. Correia,
Renato P. Ribas,
André Inácio Reis:
Comparing Transistor-Level Implementations of 4-Input Logic Functions.
IWLS 2002: 361-365 |
