ISPD 1997: Napa Valley, California, USA

• Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan:
  Faster minimization of linear wirelength for global placement. 4-11
  Electronic Edition (ACM DL) BibTeX
• Huiqun Liu, D. F. Wong:
  Network flow based multi-way partitioning with area and pin constraints. 12-17
  Electronic Edition (ACM DL) BibTeX
• Dennis J.-H. Huang, Andrew B. Kahng:
  Partitioning-based standard-cell global placement with an exact objective. 18-25
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• Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko:
  VLSI/PCB placement with obstacles based on sequence-pair. 26-31
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• Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes:
  Timing driven placement in interaction with netlist transformations. 36-41
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• R. X. T. Nijssen, C. A. J. van Eijk:
  Regular layout generation of logically optimized datapaths. 42-47
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• Glenn Holt, Akhilesh Tyagi:
  Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis. 48-53
  Electronic Edition (ACM DL) BibTeX
• Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic:
  On two-step routing for FPGAS. 60-66
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• Young-Jun Cha, Chong S. Rim, Kazuo Nakajima:
  A simple and effective greedy multilayer router for MCMs. 67-72
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• Jason Cong, Patrick H. Madden:
  Performance driven global routing for standard cell design. 73-80
  Electronic Edition (ACM DL) BibTeX
• Jun Dong Cho:
  A min-cost flow based min-cost rectilinear Steiner distance-preserving tree construction. 82-87
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• Jason Cong, Andrew B. Kahng, Kwok-Shing Leung:
  Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. 88-95
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• C. Douglass Bateman, Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky:
  Provably good routing tree construction with multi-port terminals. 96-102
  Electronic Edition (ACM DL) BibTeX
• Louis Scheffer:
  A roadmap of CAD tool changes for sub-micron interconnect problems. 104-109
  Electronic Edition (ACM DL) BibTeX
• Jeffrey L. Burns, Jack A. Feldman:
  C5M - a control logic layout synthesis system for high-performance microprocessors. 110-115
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• Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez:
  A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation. 116-121
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• A. Bertolet, K. Carpenter, Keith M. Carrig, Albert M. Chu, A. Dean, Frank D. Ferraiolo, S. Kenyon, D. Phan, John G. Petrovick, G. Rodgers, D. Willmott, T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. Andrew Scott, Richard J. Weiss:
  A pseudo-hierarchical methodology for high performance microprocessor design. 124-129
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• Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar:
  Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. 130-135
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• Nevin Kapur, Debabrata Ghosh, Franc Brglez:
  Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. 136-143
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• Fung Yu Young, D. F. Wong:
  How good are slicing floorplans?. 144-149
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• Parthasarathi Dasgupta, Susmita Sur-Kolay:
  Slicibility of rectangular graphs and floorplan optimization. 150-155
  Electronic Edition (ACM DL) BibTeX
• Michael J. Alexander:
  Power optimization for FPGA look-up tables. 156-162
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• Chris C. N. Chu, D. F. Wong:
  A matrix synthesis approach to thermal placement. 163-168
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• Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin:
  Preserving HDL synthesis hierarchy for cell placement. 169-174
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• Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi:
  EWA: exact wiring-sizing algorithm. 178-185
  Electronic Edition (ACM DL) BibTeX
• D. Zhou, X. Y. Liu:
  Minimization of chip size and power consumption of high-speed VLSI buffers. 186-191
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• Chris C. N. Chu, D. F. Wong:
  Closed form solution to simultaneous buffer insertion/sizing and wire sizing. 192-197
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• Ernest S. Kuh:
  Physical design: reminiscing and looking ahead. 206
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• T. C. Hu:
  Physical design: mathematical models and methods. 207-210
  Electronic Edition (ACM DL) BibTeX
• Raul Camposano:
  The quarter micron challenge: intergrating physical and logic design. 211
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• R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele:
  Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. 212-217
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• Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy:
  The future of logic synthesis and physical design in deep-submicron process geometries. 218-224
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• David P. LaPotin, Uttam Ghoshal, Eli Chiprout, Sani R. Nassif:
  Physical design challenges for performance. 225-226
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