| |
| 2002 | ||
|---|---|---|
| 2 | EE | Jatuchai Pangjun, Sachin S. Sapatnekar: Low-power clock distribution using multiple voltages and reduced swings. IEEE Trans. VLSI Syst. 10(3): 309-318 (2002) |
| 1999 | ||
| 1 | EE | Jatuchai Pangjun, Sachin S. Sapatnekar: Clock distribution using multiple voltages. ISLPED 1999: 145-150 |
| 1 | Sachin S. Sapatnekar | [1] [2] |