ISCAS 1993:
Chicago,
Illinois,
USA - Volume 3
1993 IEEE International Symposium on Circuits and Systems,
ISCAS 1993,
Chicago,
Illinois,
USA,
May 3-6,
1993. IEEE,
1993,
ISBN 0-7803-1281-3,
Volume 3 - VLSI and Parallel Processing
High Speed VLSI Systems:
Timing and Clock Distribution
VLSI Testing
- Abdel-Fattah Yousif, Jun Gu:
An Efficient Global Search Algorithm for Test Generation.
1499-1502 BibTeX
- Weitong Chuang, Ibrahim N. Hajj:
Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection.
1503-1506 BibTeX
- Antonio Lioy, Massimo Poncino:
On the Resetability of Synchronous Sequential Circuits.
1507-1510 BibTeX
- Soo Young Lee, Kewal K. Saluja:
Efficient Test Vectors for ISCAS Sequential Benchmark Circuits.
1511-1514 BibTeX
- Cheng-Juei Wu, Wen-Ben Jone:
On Multiple Fault Detection of Parity Checkers.
1515-1518 BibTeX
- Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu:
Functional Text Pattern Generation for Asynchronous Circuits.
1519-1522 BibTeX
- Giacomo Buonanno, Franco Fummi, Donatella Sciuto:
Functional Testing and Constrained Synthesis of Sequential Architectures.
1523-1526 BibTeX
- Bernd K. Koch, Klaus D. Müller-Glaser:
An Examination of Feedback Bridging Faults in Digital CMOS Circuits.
1527-1530 BibTeX
Model Extraction,
Interconnects & MMIC's
- Dae-Hyung Cho, S. M. Kang:
An Accurate AC Characteristic Table Look-up Model for VLSI Analog Circuits Simulation Applications.
1531-1534 BibTeX
- Chang-hoon Choi, Jin-Kyu Park, Yeong-Gil Kim, Kyung-Ho Kim, Sang-Hoon Lee:
New Model Parameter Extraction Environment for the Submicron Circuit Models.
1535-1538 BibTeX
- Sherif H. K. Embabi, R. Damodaran, R. Bhagwan, Don E. Ross:
An Accurate Delay Model for BiCMOS Gates and Off-chip Drivers.
1539-1542 BibTeX
- J. Richard Griffith, Qi-Jun Zhang, Michel S. Nakhla:
Parallel Time Domain Analysis and Optimization of Distributed VLSI Interconnects.
1543-1546 BibTeX
- Dimitri Kuznetsov, José E. Schutt-Ainé:
Difference Model Approach for the Transient Simulation of Transmission Lines.
1547-1550 BibTeX
- Corneliu A. Marinov, Pekka Neittaanmäki:
Bounds for Distributed Parameter Trees.
1551-1554 BibTeX
- Nebil Tanzi, Thomas T. Y. Wong:
Computer-aided Sensitivity Analysis of Transistor Microwave Oscillators.
1555-1558 BibTeX
VLSI Signal and Image Processing Architectures
- Yasushi Iwata, Masayuki Kawamata, Tatsuo Higuchi:
Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering.
1559-1562 BibTeX
- Ming-Hwa Sheu, Jhing-Fa Wang, Jau-Yien Lee, Lian-Ying Liu:
An Expandable Chip Desing for Gray-scale Morphological Operations.
1563-1566 BibTeX
- Jue-Hsuan Hsiao, Liang-Gee Chen, Tzi-Dar Chiueh, Chun-Te Chen:
Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate.
1567-1570 BibTeX
- Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform.
1571-1574 BibTeX
- Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen:
A Multi-phase Shared Bus Structure for the Fast Fourier Transform.
1575-1578 BibTeX
- Emmanuel Boutillon, N. Demassieux:
A Generalized Precompiling scheme for Surviving Path Memory Management in Viterbi decoders.
1579-1582 BibTeX
- Klaus Gaedke, Jens Franzen, Peter Pirsch:
A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic.
1583-1586 BibTeX
- Ming-Hwa Sheu, Jau-Yien Lee, Jhing-Fa Wang, An-Nan Suen, Lian-Ying Liu:
A High Throughput-Rate Architecture for 8*8 2-D DCT.
1578-1590 BibTeX
- Matthias Sauer, Ernst G. Bernard, Josef A. Nossek:
Block Sequential CORDIC Architectures.
1591-1594 BibTeX
Testability and BIST
- João C. Vital, José E. Franca, Nuno S. Silva:
Fully-digital Testability of a High-speed Conversion System.
1595-1598 BibTeX
- M. F. Toner, Gordon W. Roberts:
Towards Built-In-Self-Test for SNR Testing of a Mixed-Signal IC.
1599-1602 BibTeX
- Maria J. Avedillo, José M. Quintana, José L. Huertas:
Easily Testable PLA-based FSMS.
1603-1606 BibTeX
- Geetani Edirisooriya, Samantha Edirisooriya, John P. Robinson:
On the Performance of Augmented Signature Testing.
1607-1610 BibTeX
- Mohamed Jamoussi, Bozena Kaminska:
A Functional-level Testability Evaluation Using a New M-Testability.
1611-1614 BibTeX
- Chiyuan Chang, Chauchin Su:
A Universal BIST Methodology for Interconnects.
1615-1618 BibTeX
- Naim Ben Hamida, Bozena Kaminska, Yvon Savaria:
Initiability: A Measure of Sequential Testability.
1619-1622 BibTeX
- Kaushik Roy:
On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs.
1623-1626 BibTeX
Circuit Simulation
- Jiri Vlach, Ajoy Opal, Jacek Wojciechowski:
Simulation of Networks with Inconsistent Initial Conditions.
1627-1630 BibTeX
- H. Song, Dileep A. Divekar, L. Mills, P. Wang:
A Method for Improving the Efficiency of Simulating Large Electronic Circuits.
1631-1634 BibTeX
- Mi-Chang Chang, Jue-Hsien Chern, Ping Yang:
Efficient and Robust Path Tracing Algorithm for DC Convergence Problem.
1635-1638 BibTeX
- Lena Peterson, Sven Mattisson:
Dynamic Partitioning for Concurrent Waveform Relaxation-based Circuit Simulation.
1639-1642 BibTeX
- Shawki Areibi, Anthony Vannelli:
Circuit Partitioning Using a Tabu Search Approach.
1643-1646 BibTeX
- Tadashi Matsumoto, Tetsuya Sakabe, Kohkichi Tsuji:
On Parallel Symbolic Analysis of Large Networks and Systems.
1647-1650 BibTeX
- Marwan Hassoun, Prakash Atawale:
Hierarchical Symbolic Cirucit Analysis of Large-scale Networks on Multi-processor Systems.
1651-1654 BibTeX
- Roman V. Dmytryshyn:
The Use of Symbolic-numerical Methods for Electronic Circuit Analysis.
1655-1657 BibTeX
High-Level DSP Synthesis
- Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai:
A Performance-driven Approach to the High-level Synthesis of DSP Algorithms.
1658-1661 BibTeX
- Ching-Yi Wang, Keshab K. Parhi:
Loop List Scheduler for DSP Algorithms under Resource Consraints.
1662-1665 BibTeX
- Said Amellal, Bozena Kaminska:
Scheduling of a Control and Data Flow Graph.
1666-1669 BibTeX
- William Robertson, S. Periyalwar, William J. Phillips:
RTL Synthesis for Systolic Arrays.
1670-1673 BibTeX
- Samir Lejmi, Bozena Kaminska, Edouard Wagneur:
Resynthesis and Retiming of Synchronous Sequential Cirucits.
1674-1677 BibTeX
- Michael R. Rhinehart, John A. Nestor:
SALSE II: A Fast Transformational Scheduler for High-level Synthesis.
1678-1681 BibTeX
- Ian G. Harris, Alex Orailoglu:
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area.
1682-1685 BibTeX
- Ruchir Puri, Jun Gu:
Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis.
1686-1689 BibTeX
Logic Verification and Synthesis
Parallel DSP Architectures
- Xiaqi Liu, Hong Fan:
A Spatial Schur Type LS Algorithm and Its Pyramid Systolic Array Implementation.
1722-1725 BibTeX
- Scott T. Campbell, Soon Myoung Chung:
Video Decimator Design Using A Systolic Array.
1726-1729 BibTeX
- Haris M. Stellakis, Elias S. Manolakos:
Time- and Order-recursive Estimation of Higher Order Moments in a Linear Array.
1730-1733 BibTeX
- Keshab K. Parhi, Takao Nishitani:
Folded VLSI Architectures for Discrete Wavelet Transforms.
1734-1737 BibTeX
- Dimitrios Soudris, P. D. Georgakopoulos, Constantinos E. Goutis:
A Systematic Methodology for Designing Multilevel Systolic Architectures.
1738-1741 BibTeX
- Jiann-Jenn Wang, Chein-Wei Jen:
A High Throughput Systolic Design for QR Algorithm.
1742-1745 BibTeX
- L. Wang, Iiro Hartimo:
Systolic Array for 2-D Circular Convolution Using the Chinese Remainder Theorem.
1746-1749 BibTeX
- Peter Pirsch, Winfried Gehrke, R. Hoffer:
A Hierarchical Multiprocessor Achitecture for Video Coding Applications.
1750-1753 BibTeX
- Nobuyuki Yagi, Kazuo Fukui, Kazumasa Enami, Nobuyuki Sasaki, Hidetaka Saitou, Yuji Konno, Ryuichiro Tomita:
A Programmable Video Signal Multi-processor for HDTV Signals.
1754-1757 BibTeX
VLSI Floor Planning and Partitioning
- Mitsuho Seki, Shun'ichi Kobayashi, Munehiro Takubo, Kazuyoshi Kurosawa:
A New Floorplan Simultaneously Placing Blocks over Two Logic Layers for Sea-of-gate Gate Arrays.
1758-1761 BibTeX
- Kai Wang, Wai-Kai Chen:
A Class of Zero Wasted Area Floorplan for VLSI Design.
1762-1765 BibTeX
- S. C. Prasad, P. W. Kollaritsch, P. Anirudhan, D. K. Hwang, S. Lusky, R. Farrow:
Efficient Floorplan Enumeration Using Dynamic Programming.
1766-1769 BibTeX
- Nasir-ud-Din Gohar, Peter Y. K. Cheung:
A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout.
1770-1773 BibTeX
- Cheng-Hsi Chen, Ioannis G. Tollis:
A Fast Parallel Algorithm for Slicing Floorplans.
1774-1777 BibTeX
- Yao-Ping Chen, Ting-Chi Wang, D. F. Wong:
A Graph Partitioning Problem for Multiple-chip Design.
1778-1781 BibTeX
- Malgorzata Chrzanowska-Jeske, S. Goller, I. Schafer:
An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD.
1782-1785 BibTeX
Statistical Design
- Sachin S. Sapatnekar, Pravin M. Vaidya, Sung-Mo Kang:
Feasible Region Approximation Using Convex Polytopes.
1786-1789 BibTeX
- Xiao XiangMing, Robert Spence:
Speeding Design Centering By Reusing Simulated Data.
1790-1792 BibTeX
- Richard M. M. Chen, Wilson W. Chan:
An Efficient Tolerance Design Procedure for Yield Maximization Using Optimzation Techniques and Neural Network.
1793-1796 BibTeX
- Yeong-Gil Kim, Jai-Hoon Lee, Kyung-Ho Kim, Sang-Hoon Lee:
SENSATION: A New Environment for Automatic Circuit Optimization and Statistical Analysis.
1797-1801 BibTeX
- Hua Su, Mohammed Ismail, Christopher Michael:
Yield Optimzation of Analog MOS Integrated Including Transistor Mismatch.
1801-1804 BibTeX
- Jian Chen, M. A. Styblinski:
A Systematic Approach of Statistical Modeling and Its Application to CMOS Circuits.
1805-1808 BibTeX
- Ming Qu, M. A. Styblinski:
A Heursitsic Global Optimization Algorithm and Its Application to CMOS Circuit Variability Minimization.
1809-1812 BibTeX
- B. R. S. Rodrigues, M. A. Styblinski:
Adaptive Hierarchical Multi-objective Fuzzy Optimization for Circuit Design.
1813-1816 BibTeX
Computer Arithmetic
- Min C. Park, Bang W. Lee, Gwang Moon Kim, Dong H. Kim:
Compact and Fast Multiplier Using Dual Array Tree Structure.
1817-1820 BibTeX
- Seon Wook Kim, Thanos Stouraitis, Alexander Skavantzos:
Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems.
1821-1824 BibTeX
- Farhad Fuad Islam, Keikichi Tamaru:
An Architecture for Intermediate Area-time Complexity Multiplier.
1825-1828 BibTeX
- Stefan Wolter, Andreas Schubert, Holger Matz, Rainer Laur:
On the Comparison Between Architectures for the Implementation of Distributed Arithmetic.
1829-1832 BibTeX
- Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis:
Methodology for the Design of Signed-digit DSP Processors.
1833-1836 BibTeX
- Zhongde Wang, Graham A. Jullien, William C. Miller, June Wang:
New Concepts for the Design of Carry Lookahaead Adders.
1837-1840 BibTeX
- Ishaq H. Unwala, Earl E. Swartzlander Jr.:
Superpipelined Adder Designs.
1841-1844 BibTeX
VLSI Layout Styles,
Compaction,
and Routing
- Karol Doerffer, Attila T. Téby, Oskar Anton, Dieter A. Mlynski:
KLaGen - A Generator of Static CMOS-cell Layout from Circuit Schematics.
1845-1848 BibTeX
- Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang:
Layout Compaction with Minimzed Delay Bound on Timing Critical Paths.
1849-1852 BibTeX
- Oskar Anton, Karol Doerffer, Dieter A. Mlynski:
Automatic Design of Transparent Standard Cells with TRANSCAD II.
1853-1856 BibTeX
- Charles Wiley, K. M. Lau, Stephen A. Szygenda:
m3D: A Multidimensional Dynamic Configurable Router.
1857-1860 BibTeX
- Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani:
Efficient Over-the-cell Routing Algorithm for General Middle Terminal Model.
1861-1864 BibTeX
- Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
Minimum Density Interconneciton Trees.
1865-1868 BibTeX
- Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng:
A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing.
1869-1872 BibTeX
- Yu Hen Hu, Chi-Yu Mao:
Solving Gate-Matrix Layout Problems by Simulated Evolution.
1873-1876 BibTeX
Poster:
VLSI and Parallel Processing
- Hazem H. Ali, Mona E. Zaghloul:
VLSI Implementation of an Associative Memory Using Temporal Relations.
1877-1880 BibTeX
- D. K. Harris-Dowsett, S. Summerfield:
Low Latency Architectures for Wave Digital Filters.
1881-1884 BibTeX
- S. C. Chan, C. W. Kok, S. W. Chau:
Codebook Generation and Search Algorithm for Vector Quantization Using Arbitrary Hyperplanes.
1885-1888 BibTeX
- Shaw-Min Lei:
Finite Word-length Effects on Arithmetic Codes.
1889-1892 BibTeX
- Ghassan Y. Yacoub, Tarun Soni, Walter H. Ku:
A Compact Array Processor Based on Self-timed Simultaneous Bidirectional Signalling.
1893-1896 BibTeX
- Eel-Wan Lee, Jae-Hee Won, Soo-Ik Chae:
Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm.
1897-1900 BibTeX
- Laurent Letellier, Didier Juvin, Jean-Luc Basille, Jean Rebillat:
High Performance Graphics on a SIMD Linear Processor Array.
1901-1904 BibTeX
- Hong-Yi Huang, Chung-Yu Wu:
Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications.
1905-1908 BibTeX
- Clifford Sze-Tsan Choy, Wan-Chi Siu:
Generation of Chain-coded Contours and Contours Inclusion Relationship Under Multiprocessor Environment.
1909-1912 BibTeX
- C. J. Su, K. P. Lam:
Digital Circuit Implementation of a Continuous-time Inference Network for the Transitive Closure Problem.
1913-1916 BibTeX
- Spiridon Nikolaidis, D. E. Metafas, Constantinos E. Goutis:
CORDIC Based Pipeline Architecture for All-pass Filters.
1917-1920 BibTeX
- Tsuyoshi Kawaguchi:
Static Allocation of a Task Tree onto a Linear Array.
1921-1924 BibTeX
- Yi-Min Wang:
Reducing Message Logging Overhead for Log-based Recovery.
1925-1928 BibTeX
- Stephen P. S. Lam:
A New Approach to Reconfigure Faulty Systolic Array.
1929-1932 BibTeX
- Moon Key Lee, Byeong Yoon Choi, Kwang Yub Lee, Seong Ho Lee:
Data-stationary Controller for 32-bit Application-specific RISC.
1933-1936 BibTeX
- Young-Hyun Jun, Weon-Hwa Jeong, Jong-Hoon Park, Tae-Hoon Kim, Seong-Wook Kim, Jae-Sik Lee, Seong-Jin Jang, Chang-Man Khang, Hee-Gook Lee:
A New Colum Redundancy Scheme For Fast Access Time of 64-Mb DRAM.
1937-1940 BibTeX
- J. David Narkiewicz, Wayne Burleson:
Rank-order Filtering Algorithms: A Comparison of VLSI Implementations.
1941-1944 BibTeX
- Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton:
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
1945-1948 BibTeX
- Fida H. Chishti, Anthony R. Clare, Moe Razaz:
Parallel Solution of Symmetric Banded Systems on Transputers.
1949-1952 BibTeX
- Belle W. Y. Wei, Richard Tarver, Jong-Seop Kim, Kevin Ng:
A Single Chip Lempel-Ziv Data Compressor.
1953-1955 BibTeX
- Naresh R. Shanbhag, Keshab K. Parhi:
A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications.
1956-1958 BibTeX
- Kalavai J. Raghunath, Keshab K. Parhi:
High Speed RLS Using Scaled Tangent Rotations (STAR).
1959-1962 BibTeX
- Robert W. Adams, Tom Kwan:
A Monolithic Asynchronous Sample-Rate Converter for Digital Audio.
1963-1966 BibTeX
- Mark W. Mao, B. Y. Chen, James B. Kuo:
A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique.
1967-1970 BibTeX
- Hakim Khali, Jean-Louis Houle, Yvon Savaria:
A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm.
1971-1974 BibTeX
- Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder:
Architecture and VLSI Design of a VLSI Neural Signal Processor.
1975-1978 BibTeX
- K. C. Lo, Alan Purvis:
Parallel Random Sampling with Multiprocessor System.
1979-1982 BibTeX
- Karol Doerffer, Oskar Anton, Dieter A. Mlynski:
Time Efficient Method for MOS Circuit Extraction.
1983-1986 BibTeX
- Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya:
Test Generation for BiCMOS Circuits.
1987-1990 BibTeX
- Salil Raje, Majid Sarrafzadeh:
GEM: A Geometric Algorithm for Scheduling.
1991-1994 BibTeX
- Suresh Rai, Jerry L. Trahan, Thomas Smailus:
Processor Allocation in Faulty Hypercube Multiprocessors.
1995-1998 BibTeX
- K. J. Ray Liu, An-Yeu Wu:
A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation.
1999-2002 BibTeX
- Chan S. Kim, Sang W. Song, Man Y. Kim, Young T. Han, Sang A. Kang, Bang W. Lee:
200 Mega Pixel Rate IDCT Processor for HDTVC Applications.
2003-2006 BibTeX
VLSI Design and Applications
- Kenneth J. Schultz, P. Glenn Gulak:
A Logic-enhanced Memory for Digital Data Recovery Circuits.
2007-2010 BibTeX
- Srini W. Seetharam, Gary J. Minden, Joseph B. Evans:
A Parallel SONET Scrambler/Descrambler Architecture.
2011-2014 BibTeX
- Laurent Lemaitre, Marek J. Patyra:
Fuzzy Logic Functions Synthesis - A CMOS Current Mirror Based Solution.
2015-2018 BibTeX
- Manuel J. Bellido, Manuel Valencia, Antonio J. Acosta, Angel Barriga Barrios, José Luis Huertas, Rafael Domínguez-Castro:
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch.
2019-2022 BibTeX
- Mohamed Nekili, Yvon Savaria:
Parallel Regeneration of Interconnections in VLSI & ULSI Circuits.
2023-2026 BibTeX
- James B. Kuo, H. P. Chen, H. J. Huang:
A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI.
2027-2030 BibTeX
- D. Wagner, Subhash C. Kwatra, M. M. Jamali:
A Single Chip High Data Rate QPSK Demodulator.
2031-2034 BibTeX
- H. Kumar, Magdy A. Bayoumi, Akhilesh Tyagi, Nam Ling, R. Kalyan:
Parallel Implementation of a Cut and Paste Maze Routing Algorithm.
2035-2038 BibTeX
- Kuei-Ann Wen, Shihn-Cheng Chen, Jo-Tan Yao:
Single Processor Design for 2-D Wiener Filter.
2039-2042 BibTeX
VLSI Placement
Poster:
Computer-Aided Analysis,
Design and Simulation
- Christopher M. Wolff, Jung-hui Cheng:
Symbolic Precompilation of Piecewise-linear Behavioral Models for Efficient Simulation of Dual Time Scale Systems.
2075-2078 BibTeX
- Subbarao Somanchi, Mark L. Manwaring:
Analog Synthesis from Behavioural Descriptions.
2079-2082 BibTeX
- Jorge Chávez Orzáez, Miguel Angel Aguirre Echánove, Antonio Jesús Torralba Silgado:
Analog Design Optimization : A Case Study.
2083-2085 BibTeX
- Carlos A. Losada, David G. Haigh, Paul M. Radmore:
A Systematic Method for Nonlinear Analysis of a Class of FET Circuits.
2086-2089 BibTeX
- K. Wayne Current, Jim Parker, Wes Hardaker:
Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs.
2090-2093 BibTeX
- Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi:
A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits.
2094-2097 BibTeX
- Valentino Liberali, Enrico Malavasi, Davide Pandini:
Automatic Generation of Transistor Stacks for CMOS Analog Layout.
2098-2102 BibTeX
- N. S. Nagaraj:
A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing.
2102-2105 BibTeX
- Kumar Venkat:
Generalized Delay Optimization of Resistive Interconnections through an Extension of Logical Effort.
2106-2109 BibTeX
- Brian S. Cherkauer, Eby G. Friedman:
The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs.
2110-2113 BibTeX
- Perng-Shyong Lin, Charles A. Zukowski:
Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies.
2114-2117 BibTeX
- Huang Qiuting:
Speed Optimization of Edge-Triggered Nine-Transistor D-Flip-Flops for Gigahertz Single-Phase Clocks.
2118-2121 BibTeX
- José E. Schutt-Ainé, Kyung-soo Oh:
Modeling Interconnections with Nonlinear Discontinuities.
2122-2124 BibTeX
- D. S. Gao, Dian Zhou:
Propagation Delay in RLC Interconnection Networks.
2125-2128 BibTeX
- Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong:
A Two-pole Circuit Model for VLSI High-speed Interconnection.
2129-2132 BibTeX
- Richard M. M. Chen, Xing Dong Jia:
A Technique to Improve the Convergency Speed of Relaxation-based Simulations in Tightly Coupled Circuits.
2133-2136 BibTeX
- Hans Fleurkens, Pim H. W. Buurman:
Flexible Mixed-mode and Mixed-level Simulation.
2137-2140 BibTeX
- Domenico Biey, Mario Biey, Maurizio Molinaro:
SCANSA: A Computer Program for the Statistical Analysis of Switched Capacitor Networks.
2141-2144 BibTeX
- Songxin Qi, Quanrang Yang:
An Improved Random Walk Approach for Yield Optimization.
2145-2147 BibTeX
Copyright © Sat May 16 23:25:17 2009
by Michael Ley (ley@uni-trier.de)
