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Yanbin Jiang

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2001
4EEYanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji: Technology mapping for high-performance static CMOS and pass transistor logic designs. IEEE Trans. VLSI Syst. 9(5): 577-589 (2001)
1999
3EEYanbin Jiang, Sachin S. Sapatnekar: An integrated algorithm for combined placement and libraryless technology mapping. ICCAD 1999: 102-106
1998
2EEYanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim: Interleaving buffer insertion and transistor sizing into a single optimization. IEEE Trans. VLSI Syst. 6(4): 625-633 (1998)
1997
1EEJuho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar: Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. ISPD 1997: 130-135

Coauthor Index

1Cyrus Bamji [1] [2] [4]
2Juho Kim [1] [2]
3Sachin S. Sapatnekar [1] [2] [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)