| |
| 2004 | ||
|---|---|---|
| 4 | EE | Tao Jiang, Eric Pettus, Daksh Lehther: A mixed-mode extraction flow for high performance microprocessors. ASP-DAC 2004: 697-701 |
| 1999 | ||
| 3 | Bogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick: Efficient RLC Macromodels for Digital IC Interconnect. VLSI 1999: 293-304 | |
| 1997 | ||
| 2 | EE | Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela: Clock Distribution Methodology for PowerPCTM Microprocessors. VLSI Signal Processing 16(2-3): 181-189 (1997) |
| 1996 | ||
| 1 | EE | Daksh Lehther, Sachin S. Sapatnekar: Clock tree synthesis for multi-chip modules. ICCAD 1996: 50-53 |
| 1 | Ross Baldick | [3] |
| 2 | Shantanu Ganguly | [2] |
| 3 | Tao Jiang | [4] |
| 4 | Madhulima Pandey | [3] |
| 5 | Eric Pettus | [4] |
| 6 | Satyamurthy Pullela | [2] |
| 7 | Sachin S. Sapatnekar | [1] |
| 8 | Bogdan Tutuianu | [3] |