11. IWLS 2002:
New Orleans,
Louisiana,
USA
IWLS-02,
11th IEEE/ACM International Workshop on Logic & Synthesis,
June 4-7,
2002,
New Orleans,
Louisiana,
USA. IEEE Computer Society & ACM SIGDA
Structured Logic Synthesis
- Prabhakar Kudva, Andrew Sullivan, William E. Dougherty:
Metrics for Structural Logic Synthesis.
1-6 BibTeX
- Fan Mo, Robert K. Brayton:
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design.
7-12 BibTeX
- Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically Constrained Logic Synthesis.
13-20 BibTeX
- Anas Al-Rabadi, Lee W. Casperson:
Optical Realizations of Reversible Logic.
21-26 BibTeX
- Theodore W. Manikas, Gerald R. Kane:
Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement.
27-30 BibTeX
- Pawel Kerntopf:
An Approach to Designing Complex Reversible Logic Gates.
31-36 BibTeX
- Mohamed A. Elgamel, Magdy A. Bayoumi:
On Low Power High Level Synthesis Using Genetic Algorithms.
37-40 BibTeX
- Hua Tang, Alex Doboli:
Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing.
41-44 BibTeX
- Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.
45-50 BibTeX
- Tomas Bengtsson, Andrés Martinelli, Elena Dubrova:
A Fast Heuristic Algorithm for Disjunctive.
51-56 BibTeX
- Nattawut Thepayasuwan, Alex Doboli:
A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints.
57-60 BibTeX
- Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
An Efficient Two-Level Filter Scheme for Low Power Cache.
61-66 BibTeX
- Svetlana N. Yanushkevich, Vlad P. Shmerko, V. D. Malyugin, Piotr Dziurzanski:
Linearity of World-Level Circuit Models: New Understanding.
67-72 BibTeX
- Jorgiano Vidal, David Déharbe, Dominique Borrione:
Improving Static Ordering of BDDs for Reachability Analysis.
73-77 BibTeX
- Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain:
Improving Sequential ATPG Using SAT Methods.
79-84 BibTeX
- Pawel Kerntopf:
Nonlinear Sifting of Decision Diagrams.
85-90 BibTeX
Reconfigurable Architectures
- Jason Cong, Joey Y. Lin, Wangning Long:
Enhanced SPFD Rewiring on Improving Rewiring Ability.
91-96 BibTeX
- Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz:
A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification.
97-102 BibTeX
- Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.
103-108 BibTeX
- Silviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton:
Synthesis of Morphable Multipliers.
109-113 BibTeX
- Alan Mishchenko, Tsutomu Sasao:
Encoding of Boolean Functions and its Application to LUT Cascade Synthesis.
115-120 BibTeX
Novel Design Styles
Poster Session #2
- Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah:
ZBDD-Based Backtrack Search SAT Solver.
131-136 BibTeX
- Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Efficient Gate and Input Ordering for Circuit-to-BDD Conversion.
137-142 BibTeX
- Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton:
Low Power Optimization Techniques for BDD Mapped Finite State Machines.
143-148 BibTeX
- Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou:
A Practical Approach to Cycle Bound Estimation for Property Checking.
149-154 BibTeX
- Agnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev:
Visualization of Coding Conflicts in Asynchronous Circuit Design.
155-160 BibTeX
- S. G. Gibb, Laurence E. Turner:
The Automatic Generation of Application Specific Processors.
161-165 BibTeX
- Loïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan:
A LUT based Approach for High Level Synthesis on FPGAs.
167-172 BibTeX
- Alan Mishchenko, Robert K. Brayton:
A Boolean Paradigm in Multi-Valued Logic Synthesis.
173-177 BibTeX
- Leyla Nazhandali, Karem A. Sakallah:
Majority-Based Decomposition of Carry Logic in Binary Adders.
179-184 BibTeX
- Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Simplifying Constraint Solving in Random Simulation Generation.
185-190 BibTeX
- Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin:
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net.
191-196 BibTeX
- Alan Mishchenko, Marek A. Perkowski:
Logic Synthesis of Reversible Wave Cascades.
197-202 BibTeX
Custom,
PTL and Dynamic Circuits
Restructuring Logic Transformations
Poster Session #3
- Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala:
On-line Error Detection in a Carry-free Adder.
251-254 BibTeX
- Amit Tandon, Federico Politi:
Model Generation and Gate Level Abstraction of Complex CMOS Custom Design for Functional and DFT Validation.
255-260 BibTeX
- Andrei B. Khlopotine, Marek A. Perkowski, Pawel Kerntopf:
Reversible Logic Synthesis by Iterative Compositions.
261-266 BibTeX
- Ankur Srivastava, Majid Sarrafzadeh:
Predictability: Definition, Analysis and Optimization.
267-272 BibTeX
- Anas Al-Rabadi:
Symmetry as a Base for a New Decomposition of Boolean Logic.
273-278 BibTeX
- Masayuki Tsukisaka, Masashi Imai, Takashi Nanya:
High Throughput Asynchronous Domino Using Dual output Buffer.
279-282 BibTeX
- Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera:
Experimental Study on Cell-Base High-Performance Datapath Design.
283-287 BibTeX
- Geun Rae Cho, Tom Chen:
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis.
289-294 BibTeX
- Chang Woo Kang, Massoud Pedram:
Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration.
295-300 BibTeX
Analysis Techniques
Don't Cares and Logic Optimization
Poster Session #4
SAT and BDD's
Optical and Mixed-Technology Systems:
Where Election Meet Laser Beams
High-Level Language and Synthesis
Power Issues
Copyright © Sat May 16 23:27:19 2009
by Michael Ley (ley@uni-trier.de)