IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 11

Volume 11, Number 1, February 2003

• Phillip Christie:
  Guest editorial: System-level interconnect prediction. 1-2
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• Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester:
  Improved a priori interconnect predictions and technology extrapolation in the GTX system. 3-14
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• Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie:
  Multi-objective optimization of interconnect geometry. 15-23
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• J. Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout:
  A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits. 24-34
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• Dirk Stroobandt:
  A priori wire length distribution models with multiterminal nets. 35-43
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• Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif:
  Wiring requirement and three-dimensional integration technology for field programmable gate arrays. 44-54
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• Phillip Christie, José Pineda de Gyvez:
  Prelayout interconnect yield prediction. 55-59
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• M. Hutton, K. Adibsamii, A. Leaver:
  Adaptive delay estimation for partitioning-driven PLD placement. 60-63
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• Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
  Energy-efficient skewed static logic with dual Vt: design and synthesis. 64-70
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• Abdel Ejnioui, N. Ranganathan:
  Multiterminal net routing for partial crossbar-based multi-FPGA systems. 71-78
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• Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
  Noise-aware interconnect power optimization in domino logic synthesis. 79-89
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• M. P. Leong, Philip Heng Wai Leong:
  A variable-radix digit-serial design methodology and its application to the discrete cosine transform. 90-104
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• Arindam Mukherjee, Malgorzata Marek-Sadowska:
  Wave steering to integrate logic and physical syntheses. 105-120
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• Michael Nicolaidis:
  Carry checking/parity prediction adders and ALUs. 121-128
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• Ken S. Stevens, Ran Ginosar, Shai Rotem:
  Relative timing [asynchronous design]. 129-140
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• T. J. Thorp, G. S. Yee, C. M. Sechen:
  Design and synthesis of dynamic circuits. 141-149
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• Kyung-Saeng Kim, Kwyro Lee:
  Low-power and area-efficient FIR filter implementation suitable for multiple taps. 150-153
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Volume 11, Number 2, April 2003

• David Blaauw, Supamas Sirichotiyakul, Chanhee Oh:
  Driver modeling and alignment for worst-case delay noise. 157-166
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• K. Chakrabarty:
  A synthesis-for-transparency approach for hierarchical and system-on-a-chip test. 167-179
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• Payam Heydari, Massoud Pedram:
  Ground bounce in digital VLSI circuits. 180-193
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• Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou:
  A true single-phase energy-recovery multiplier. 194-207
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• Surin Kittitornkun, Yu Hen Hu:
  Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures. 208-217
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• Kyung-suc Nah, Byeong-ha Park:
  A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply. 218-223
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• Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
  Maximizing throughput over parallel wire structures in the deep submicrometer regime. 224-243
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• Jongsun Park, Khurram Muhammad, Kaushik Roy:
  High-performance FIR filter design based on sharing multiplication. 244-253
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• Lei Wang, Naresh R. Shanbhag:
  Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. 254-269
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• Ali Manzak, Chaitali Chakrabarti:
  Variable voltage task scheduling algorithms for minimizing energy/power. 270-276
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• R. Hossain, F. Viglione, M. Cavalli:
  Designing fast on-chip interconnects for deep submicrometer technologies. 276-280
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• Uwe Meyer-Bäse, Thanos Stouraitis:
  New power-of-2 RNS scaling scheme for cell-based IC design. 280-283
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• Abdel Ejnioui, N. Ranganathan:
  Routing on field-programmable switch matrices. 283-287
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• Hanho Lee:
  High-speed VLSI architecture for parallel Reed-Solomon decoder. 288-294
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• D. Harris, S. Naffziger:
  Correction to "statistical clock skew modeling with data delay variations". 295-296
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Volume 11, Number 3, June 2003

• Yiannos Manoli:
  Special section on the 2001 International Conference on Computer Design (ICCD). 301-302
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• Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger:
  Static energy reduction techniques for microprocessor caches. 303-313
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• Lu Peng, Jih-Kwon Peir, Qianrong Ma, Konrad Lai:
  Address-free memory access based on program syntax correlation of loads and stores. 314-324
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• John Patrick McGregor, Ruby B. Lee:
  Architectural techniques for accelerating subword permutations with repetitions. 325-335
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• Yu Zheng, Kenneth L. Shepard:
  On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits. 336-344
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• Jin Yang, Carl-Johan H. Seger:
  Introduction to generalized symbolic trajectory evaluation. 345-353
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• Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska:
  PITIA: an FPGA for throughput-intensive applications. 354-363
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• Chun-Gi Lyuh, Taewhan Kim:
  High-level synthesis for low power based on network flow method. 364-375
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• Frederik Vermeulen, Francky Catthoor, Lode Nachtergaele, Diederik Verkest, Hugo De Man:
  Power-efficient flexible processor architecture for embedded applications. 376-385
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• Abderrahim Doumar, Hideo Ito:
  Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. 386-405
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• Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
  Current-mode signaling in deep submicrometer global interconnects. 406-417
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• Oscal T.-C. Chen, Sandy Wang, Yi-Wen Wu:
  Minimization of switching activities of partial products for designing low-power multipliers. 418-433
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• Lei Wang, Naresh R. Shanbhag:
  Low-power MIMO signal processing. 434-445
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• Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis, Constantinos E. Goutis:
  Power efficient data path synthesis of sum-of-products computations. 446-450
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• Yu-Liang Wu, Chak-Chung Cheung, David Ihsin Cheng, Hongbing Fan:
  Further improve circuit partitioning using GBAW logic perturbation techniques. 451-460
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• Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer:
  Buffer delay change in the presence of power and ground noise. 461-473
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• Jin-Hua Hong, Cheng-Wen Wu:
  Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. 474-484
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• Xuejun Liang, Jack S. N. Jean:
  Mapping of generalized template matching onto reconfigurable computers. 485-498
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• J. L. Nunez, S. Jones:
  Gbit/s lossless data compression hardware. 499-510
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• Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola:
  Board-level multiterminal net assignment for the partial cross-bar architecture. 511-514
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• Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
  Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. 514-522
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Volume 11, Number 4, August 2003

• Subodh Gupta, Farid N. Najm:
  Energy and peak-current per-cycle estimation at RTL. 525-537
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• Anand Raghunathan, Sujit Dey, Niraj K. Jha:
  High-level macro-modeling and estimation techniques for switching activity and power consumption. 538-557
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• Sanjukta Bhanja, N. Ranganathan:
  Switching activity estimation of VLSI circuits using Bayesian networks. 558-567
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• Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai:
  Design and analysis of low-power cache using two-level filter scheme. 568-580
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• Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen:
  An area-saving decoder structure for ROMs. 581-589
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• Byung-Do Yang, Lee-Sup Kim:
  A low-power charge-recycling ROM architecture. 590-600
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• George Hadjiyiannis, Srinivas Devadas:
  Techniques for accurate performance evaluation in architecture exploration. 601-615
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• Y. Elboim, Avinoam Kolodny, Ran Ginosar:
  A clock-tuning circuit for system-on-chip. 616-626
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• Mohammad M. Mansour, Naresh R. Shanbhag:
  VLSI architectures for SISO-APP decoders. 627-650
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• Shih-Chang Hsia:
  Parallel VLSI design for a real-time video-impulse noise-reduction processor. 651-658
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• Gaye Lightbody, Roger Woods, Richard Walke:
  Design of a parameterizable silicon intellectual property core for QR-based RLS filtering. 659-678
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• Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin:
  Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. 679-686
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• Hong-Sik Kim, YongJoon Kim, Sungho Kang:
  Test-decompression mechanism using a variable-length multiple-polynomial LFSR. 687-690
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• Ting-Yuan Wang, Charlie Chung-Ping Chen:
  Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method. 691-700
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• Navid Azizi, Farid N. Najm, Andreas Moshovos:
  Low-leakage asymmetric-cell SRAM. 701-715
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• Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy:
  Gate leakage reduction for scaled devices using transistor stacking. 716-730
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• Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau:
  RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions. 731-737
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• Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang:
  Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm. 737-740
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• Sujit T. Zachariah, Sreejit Chakravarty:
  Algorithm to extract two-node bridges. 741-744
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• T. Thorp, D. Liu, P. Trivedi:
  Analysis of blocking dynamic circuits. 744-748
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Volume 11, Number 5, October 2003

• Vivek De, Luca Benini:
  Guest editorial. 753-754
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• Hyunsik Im, T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai:
  VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. 755-761
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• Joong-Seok Moon, William C. Athas, Sigfrid D. Soli, Jeffrey T. Draper, Peter A. Beerel:
  Voltage-pulse driven harmonic resonant rail drivers for low-power applications. 762-777
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• Victor V. Zyuban:
  Optimization of scannable latches for low energy. 778-788
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• Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter M. Kogge:
  Energy-efficient issue queue design. 789-800
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• Baruch Solomon, Avi Mendelson, Ronny Ronen, Doron Orenstein, Yoav Almog:
  Micro-operation cache: a power aware frontend for variable instruction length ISA. 801-811
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• Johan A. Pouwelse, Koen Langendoen, Henk J. Sips:
  Application-directed voltage scaling. 812-826
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• Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt:
  Adaptive low-power address encoding techniques using self-organizing lists. 827-834
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• M. A. I. Mostafa, Sherif H. K. Embabi, Mostafa Elmala:
  A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers. 835-838
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• Mandeep Singh, Israel Koren:
  Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters. 839-852
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• Sungbae Hwang, Jacob A. Abraham:
  Test data compression and test time reduction using an embedded microprocessor. 853-862
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• Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De:
  Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. 863-870
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• Mohammad Maymandi-Nejad, Manoj Sachdev:
  A digitally programmable delay element: design and analysis. 871-878
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• Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang:
  Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. 879-887
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• T. Chen, S. Naffziger:
  Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation. 888-899
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• Yehea I. Ismail:
  Improved model-order reduction by using spacial information in moments. 900-908
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• Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills:
  Modeling technology impact on cluster microprocessor performance. 909-920
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• Ashok K. Murugavel, N. Ranganathan:
  Petri net modeling of gate and interconnect delays for power estimation. 921-927
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• Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda:
  Memory allocation and mapping in high-level synthesis - an integrated approach. 928-938
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• Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
  A high-speed energy-efficient 64-bit reconfigurable binary adder. 939-943
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• Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf:
  A dictionary-based en/decoding scheme for low-power data buses. 943-951
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• Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura:
  Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. 951-954
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• Sandeep Koranne:
  Design of reconfigurable access wrappers for embedded core based SoC test. 955-960
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Volume 11, Number 6, December 2003

• Xun Liu, Marios C. Papaefthymiou:
  Design of a 20-mb/s 256-state Viterbi decoder. 965-975
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• Mohammad M. Mansour, Naresh R. Shanbhag:
  High-throughput LDPC decoders. 976-996
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• Woo-Suk Ko, Joon-Seok Kim, Young-Cheol Park, Tai-Ho Koh, Dae Hee Youn:
  An efficient DMT modem for the G.LITE ADSL transceiver. 997-1005
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• Joohee Kim, Marios C. Papaefthymiou:
  Block-based multiperiod dynamic memory design for low data-retention power. 1006-1018
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• Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach:
  A model for battery lifetime analysis for organizing applications on a pocket computer. 1019-1030
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• Ashok K. Murugavel, N. Ranganathan:
  A game theoretic approach for power optimization during behavioral synthesis. 1031-1043
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• Amit Sinha, Nathan Ickes, Anantha P. Chandrakasan:
  Instruction level and operating system profiling for energy exposed software. 1044-1057
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• C. H.-I. Kim, Hendrawan Soeleman, Kaushik Roy:
  Ultra-low-power DLMS adaptive filter for hearing aid applications. 1058-1067
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• Qinwei Xu, Pinaki Mazumder:
  Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods. 1068-1079
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• Volkan Kursun, Eby G. Friedman:
  Domino logic with variable threshold voltage keeper. 1080-1093
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• Shrirang K. Karandikar, Sachin S. Sapatnekar:
  Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. 1094-1105
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• Rajiv V. Joshi, Ching-Te Chuang, S. K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi:
  PD/SOI SRAM performance in presence of gate-to-body tunneling current. 1106-1113
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• T. Felicijan, Stephen B. Furber:
  An asynchronous ternary logic signaling system. 1114-1119
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• Saurabh N. Adya, Igor L. Markov:
  Fixed-outline floorplanning: enabling hierarchical design. 1120-1135
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• Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
  Scheduling battery usage in mobile systems. 1136-1143
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• M. A. Azadpour, T. S. Kalkur:
  A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect. 1143-1146
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• Li Ding, Pinaki Mazumder:
  Simultaneous switching noise analysis using application specific device modeling. 1146-1152
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• O. Milter, Avinoam Kolodny:
  Crosstalk noise reduction in synthesized digital logic circuits. 1153-1158
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