Jatan C. Shah
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1996
1
EE
Jatan C. Shah,
Sachin S. Sapatnekar
: Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.
VLSI Design 1996
: 346-351
Coauthor
Index
1
Sachin S. Sapatnekar
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1
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Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
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