Volume 8,
Number 1,
February 2000
- Yanbing Li, Miriam Leeser:
HML, a novel hardware description language and its translation to VHDL.
1-8
Electronic Edition (link) BibTeX
- Farzan Fallah, Stan Y. Liao, Srinivas Devadas:
Solving covering problems using LPR-based lower bounds.
9-17
Electronic Edition (link) BibTeX
- Subodh Gupta, Farid N. Najm:
Power modeling for high-level power estimation.
18-29
Electronic Edition (link) BibTeX
- Mohammed A. S. Khalid, Jonathan Rose:
A novel and efficient routing architecture for multi-FPGA systems.
30-39
Electronic Edition (link) BibTeX
- Darko Kirovski, Miodrag Potkonjak, Lisa M. Guerra:
Cut-based functional debugging for programmable systems-on-chip.
40-51
Electronic Edition (link) BibTeX
- Jer-Min Jou, Pei-Yin Chen, Sheng-Fu Yang:
An adaptive fuzzy logic controller: its VLSI architecture and applications.
52-60
Electronic Edition (link) BibTeX
- Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng:
Estimation for maximum instantaneous current through supply lines for CMOS circuits.
61-73
Electronic Edition (link) BibTeX
- Song Chen, Adam Postula:
Synthesis of custom interleaved memory systems.
74-83
Electronic Edition (link) BibTeX
- Alexander Marquardt, Vaughn Betz, Jonathan Rose:
Speed and area tradeoffs in cluster-based FPGA architectures.
84-93
Electronic Edition (link) BibTeX
- Uming Ko, Poras T. Balsara:
High-performance energy-efficient D-flip-flop circuits.
94-98
Electronic Edition (link) BibTeX
- Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto:
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions.
98-103
Electronic Edition (link) BibTeX
- Wei-Chang Tsai, C. B. Shung, Sheng-Jyh Wang:
Two systolic architectures for modular multiplication.
103-107
Electronic Edition (link) BibTeX
Volume 8,
Number 2,
April 2000
- Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois:
Design of self-checking fully differential circuits and boards.
113-128
Electronic Edition (link) BibTeX
- Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen:
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design.
129-137
Electronic Edition (link) BibTeX
- Scott Hauck, Matthew M. Hosler, Thomas W. Fry:
High-performance carry chains for FPGA's.
138-147
Electronic Edition (link) BibTeX
- Janardhan H. Satyanarayana, Keshab K. Parhi:
Theoretical analysis of word-level switching activity in the presence of glitching and correlation.
148-159
Electronic Edition (link) BibTeX
- Leilei Song, Keshab K. Parhi, Ichiro Kuroda, Takao Nishitani:
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs.
160-172
Electronic Edition (link) BibTeX
- Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong-Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung:
MetaCore: an application-specific programmable DSP development system.
173-183
Electronic Edition (link) BibTeX
- Johnny Öberg, Anshul Kumar, Ahmed Hemani:
Grammar-based hardware synthesis from port-size independent specifications.
184-194
Electronic Edition (link) BibTeX
- Yehea I. Ismail, Eby G. Friedman:
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.
195-206
Electronic Edition (link) BibTeX
- Frederik Vermeulen, Francky Catthoor, Diederik Verkest, Hugo De Man:
Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications.
207-216
Electronic Edition (link) BibTeX
- David Kinniment, Alexandre Yakovlev, B. Gao:
Synchronous and asynchronous A-D conversion.
217-220
Electronic Edition (link) BibTeX
- Ronald D. Blanton, John P. Hayes:
On the design of fast, easily testable ALU's.
220-223
Electronic Edition (link) BibTeX
- Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Path delay fault simulation of sequential circuits.
223-228
Electronic Edition (link) BibTeX
Volume 8,
Number 3,
June 2000
- K. Roy, D. T. Lee:
Guest editorial: low-power electronics and design.
233-234
Electronic Edition (link) BibTeX
- Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl:
A minimum total power methodology for projecting limits on CMOS GSI.
235-251
Electronic Edition (link) BibTeX
- Abram P. Dancy, Rajeevan Amirtharajah, Anantha P. Chandrakasan:
High-efficiency multiple-output DC-DC conversion for low-voltage systems.
252-263
Electronic Edition (link) BibTeX
- Hui Zhang, George Varghese, Jan M. Rabaey:
Low-swing on-chip signaling techniques: effectiveness and robustness.
264-272
Electronic Edition (link) BibTeX
- J. Y. F. Tong, David Nagle, Rob A. Rutenbar:
Reducing power by optimizing the necessary precision/range of floating-point arithmetic.
273-286
Electronic Edition (link) BibTeX
- Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Glitch power minimization by selective gate freezing.
287-298
Electronic Edition (link) BibTeX
- Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
A survey of design techniques for system-level dynamic power management.
299-316
Electronic Edition (link) BibTeX
- Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, G. Stamoulis:
Architectural and compiler techniques for energy reduction in high-performance microprocessors.
317-326
Electronic Edition (link) BibTeX
- Sari L. Coumeri, Donald E. Thomas:
Memory modeling for system synthesis.
327-334
Electronic Edition (link) BibTeX
- Diana Marculescu, Radu Marculescu, Massoud Pedram:
Theoretical bounds for switching activity analysis in finite-state machines.
335-339
Electronic Edition (link) BibTeX
- B. A. White, Mohamed I. Elmasry:
Low-power design of decimation filters for a digital IF receiver.
339-345
Electronic Edition (link) BibTeX
- Dinesh Bhatia, James Haralambides:
Resource requirements and layouts for field programmable interconnection chips.
346-355
Electronic Edition (link) BibTeX
- Kenneth Y. Yun, Kevin W. James, R. H. Fairlie-Cuninghame, Supratik Chakraborty, Rene L. Cruz:
A self-timed real-time sorting network.
356-363
Electronic Edition (link) BibTeX
Volume 8,
Number 4,
August 2000
- Jian Li, R. K. Gupta:
HDL presynthesis optimizations using a tabular model.
369-378
Electronic Edition (link) BibTeX
- Rajamohana Hegde, Naresh R. Shanbhag:
Toward achieving energy efficiency in presence of deep submicron noise.
379-391
Electronic Edition (link) BibTeX
- Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
392-400
Electronic Edition (link) BibTeX
- Toshiaki Miyazaki, Atsushi Takahara, Takahiro Murooka, Masaru Katayama, Takaki Ichimori, Kazuhiro Shirakawa, Akihiro Tsutsui, K. Fukami:
PROTEUS-Lite project: dedicated to developing a telecommunication-oriented FPGA and its applications.
401-414
Electronic Edition (link) BibTeX
- Alessandro Bogliolo, Michele Favalli, Maurizio Damiani:
Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters.
415-419
Electronic Edition (link) BibTeX
- H. T. Nguyen, A. Chattejee:
Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis.
419-424
Electronic Edition (link) BibTeX
- Gin Yee, Carl Sechen:
Clock-delayed domino for dynamic circuit design.
425-430
Electronic Edition (link) BibTeX
- Mehrdad Nourani, Christos A. Papachristou:
Stability-based algorithms for high-level synthesis of digital ASICs.
431-435
Electronic Edition (link) BibTeX
- Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Peak power estimation of VLSI circuits: new peak power measures.
435-439
Electronic Edition (link) BibTeX
- Oscal T.-C. Chen, Wei-Lung Liu:
An FIR processor with programmable dynamic data ranges.
440-446
Electronic Edition (link) BibTeX
- Samuel Norman Hamilton, Alex Orailoglu:
On-line test for fault-secure fault identification.
446-452
Electronic Edition (link) BibTeX
- Eckart Zitzler, Jürgen Teich, S. S. Bhattclcharyya:
Evolutionary algorithms for the synthesis of embedded software.
452-455
Electronic Edition (link) BibTeX
- J. Pihl:
Design automation with the TSPC circuit technique: a high-performance wave digital filter.
456-460
Electronic Edition (link) BibTeX
- Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current:
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.
460-463
Electronic Edition (link) BibTeX
Volume 8,
Number 5,
October 2000
- Allen C.-H. Wu, Nikil D. Dutt:
Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98).
469-471
Electronic Edition (link) BibTeX
- Petru Eles, Alex Doboli, Paul Pop, Zebo Peng:
Scheduling with bus access optimization for distributed embedded systems.
472-491
Electronic Edition (link) BibTeX
- Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha:
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages.
492-502
Electronic Edition (link) BibTeX
- Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu:
Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core.
503-516
Electronic Edition (link) BibTeX
- Ying Zhao, Sharad Malik:
Exact memory size estimation for array computations.
517-521
Electronic Edition (link) BibTeX
- Wonyong Sung, Soonhoi Ha:
Memory efficient software synthesis with mixed coding style from dataflow graphs.
522-526
Electronic Edition (link) BibTeX
- Dominique Borrione, Julia Dushina, Laurence V. Pierre:
A compositional model for the functional verification of high-level synthesis results.
526-530
Electronic Edition (link) BibTeX
- Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain:
Expression-tree-based algorithms for code compression on embedded RISC architectures.
530-533
Electronic Edition (link) BibTeX
- Bassam Shaer, Sami A. Al-Arian, David L. Landis:
Partitioning sequential circuits for pseudoexhaustive testing.
534-541
Electronic Edition (link) BibTeX
- Montek Singh, Steven M. Nowick:
Synthesis for logical initializability of synchronous finite-state machines.
542-557
Electronic Edition (link) BibTeX
- Christian Pacha, U. Auer, C. Burwick, Peter Glösekötter, A. Brennemann, W. Prost, F.-J. Tegude, K. F. Goser:
Threshold logic circuit design of parallel adders using resonant tunneling devices.
558-572
Electronic Edition (link) BibTeX
- Allen E. Sjogren, Chris J. Myers:
Interfacing synchronous and asynchronous modules within a high-speed pipeline.
573-583
Electronic Edition (link) BibTeX
- Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram:
Improving the efficiency of Monte Carlo power estimation [VLSI].
584-593
Electronic Edition (link) BibTeX
- Han Bin Kim, Dong Sam Ha, Takeshi Takahashi, Takahiro J. Yamaguchi:
A new approach to built-in self-testable datapath synthesis based on integer linear programming.
594-605
Electronic Edition (link) BibTeX
- F. Caignet, S. D.-B. Dhia, E. Sicard:
On the measurement of crosstalk in integrated circuits.
606-609
Electronic Edition (link) BibTeX
- Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik:
Line coverage of path delay faults.
610-614
Electronic Edition (link) BibTeX
- Pasquale Corsonello, Stefania Perri, G. Cororullo:
Area-time-power tradeoff in cellular arrays VLSI implementations.
614-624
Electronic Edition (link) BibTeX
- Antonio G. M. Strollo, E. Napoli, C. Cimino:
Analysis of power dissipation in double edge-triggered flip-flops.
624-629
Electronic Edition (link) BibTeX
- Chingwei Yeh, Yin-Shuin Kang:
Cell-based layout techniques supporting gate-level voltage scaling for low power.
629-633
Electronic Edition (link) BibTeX
- Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar:
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.
633-636
Electronic Edition (link) BibTeX
Volume 8,
Number 6,
December 2000
- P. Christie, Dirk Stroobandt:
The interpretation and application of Rent's rule.
639-648
Electronic Edition (link) BibTeX
- Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.
649-659
Electronic Edition (link) BibTeX
- Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl:
Heterogeneous architecture models for interconnect-motivated system design.
660-670
Electronic Edition (link) BibTeX
- Arifur Rahman, Rafael Reif:
System-level performance evaluation of three-dimensional integrated circuits.
671-678
Electronic Edition (link) BibTeX
- P. Christie:
Rent exponent prediction methods.
679-688
Electronic Edition (link) BibTeX
- Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl:
A compact physical via blockage model.
689-692
Electronic Edition (link) BibTeX
- Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in general purpose processors.
693-708
Electronic Edition (link) BibTeX
- Gayles Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin:
The design of the MGAP-2: a micro-grained massively parallel array.
709-716
Electronic Edition (link) BibTeX
- Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins:
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions.
717-723
Electronic Edition (link) BibTeX
- S. Chattopadhyay, S. Adhikari, S. Sengupta, M. Pal:
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier.
724-735
Electronic Edition (link) BibTeX
- Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Improving path delay testability of sequential circuits.
736-741
Electronic Edition (link) BibTeX
- D. L. Hung, H. D. Cheng, S. Sengkhamyong:
Design of a configurable accelerator for moment computation.
741-746
Electronic Edition (link) BibTeX
- Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths.
747-750
Electronic Edition (link) BibTeX
- Bassam Shaer, David L. Landis, Sami A. Al-Arian:
Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits.
750-754
Electronic Edition (link) BibTeX
Copyright © Sun May 17 00:30:59 2009
by Michael Ley (ley@uni-trier.de)