| 2000 |
|---|
| 16 | EE | Ananta K. Majhi,
V. D. Agrawak,
James Jacob,
Lalit M. Patnaik:
Line coverage of path delay faults.
IEEE Trans. VLSI Syst. 8(5): 610-614 (2000) |
| 1998 |
|---|
| 15 | EE | Pramit Chavda,
James Jacob,
Vishwani D. Agrawal:
Optimizing Logic Design Using Boolean Transforms.
VLSI Design 1998: 218-221 |
| 14 | EE | P. Srinivasa Rao,
James Jacob:
A Fast Two-level Logic Minimizer.
VLSI Design 1998: 528-533 |
| 1997 |
|---|
| 13 | EE | James Jacob,
P. Srinivas Sivakumar,
Vishwani D. Agrawal:
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs.
VLSI Design 1997: 514-515 |
| 1996 |
|---|
| 12 | EE | Nripendra N. Biswas,
C. Srikanth,
James Jacob:
Cubical CAMP for minimization of Boolean functions.
VLSI Design 1996: 264-269 |
| 11 | EE | Ananta K. Majhi,
James Jacob,
Lalit M. Patnaik,
Vishwani D. Agrawal:
On test coverage of path delay faults.
VLSI Design 1996: 418-421 |
| 10 | EE | Mandyam-Komar Srinivas,
James Jacob,
Vishwani D. Agrawal:
Functional test generation for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 831-843 (1996) |
| 1995 |
|---|
| 9 | EE | Ananta K. Majhi,
James Jacob,
Lalit M. Patnaik,
Vishwani D. Agrawal:
An efficient automatic test generation system for path delay faults in combinational circuits.
VLSI Design 1995: 161-165 |
| 8 | EE | Jacob Augustine,
Wen Feng,
James Jacob:
Logic minimization based approach for compressing image data.
VLSI Design 1995: 225-228 |
| 7 | EE | Mandyam-Komar Srinivas,
James Jacob,
Vishwani D. Agrawal:
Functional test generation for non-scan sequential circuits.
VLSI Design 1995: 47-52 |
| 1994 |
|---|
| 6 | | P. R. Suresh Kumar,
James Jacob,
Mandyam-Komar Srinivas,
Vishwani D. Agrawal:
An Improved Deductive Fault Simulator.
VLSI Design 1994: 307-310 |
| 1993 |
|---|
| 5 | | P. R. Suresh Kumar,
Mandyam-Komar Srinivas,
James Jacob:
Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation.
VLSI Design 1993: 104 |
| 1992 |
|---|
| 4 | | Mandyam-Komar Srinivas,
James Jacob,
Vishwani D. Agrawal:
Finite State Machine Testing Based on Growth and Dissappearance Faults.
FTCS 1992: 238-245 |
| 3 | EE | James Jacob,
Vishwani D. Agrawal:
Multiple fault detection in two-level multi-output circuits.
J. Electronic Testing 3(2): 171-173 (1992) |
| 1990 |
|---|
| 2 | | James Jacob,
Nripendra N. Biswas:
Further Comments on "Detection of Faults in Programmable Logic Arrays".
IEEE Trans. Computers 39(1): 155-157 (1990) |
| 1985 |
|---|
| 1 | | James Jacob,
Nripendra N. Biswas:
: A Testable PLA Design with Minimal Hardware and Test Set.
ITC 1985: 583-588 |
