Volume 6,
Number 1,
February 1995
- Vishwani D. Agrawal:
Editorial.
5-6
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- Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults.
7-22
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- Shyang-Tai Su, Rafic Z. Makki, Troy Nagle:
Transient power supply current monitoring - A new test method for CMOS VLSI circuits.
23-43
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- Konstantin Keutner, Erwin Trischler:
Efficient sensitization of multi-bit-paths for testing embedded modules in synchronous sequential circuits.
45-58
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- Kent L. Einspahr, Sharad C. Seth:
A switch-level test generation system for synchronous and asynchronous circuits.
59-73
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- D. Lambidonis, Vinod K. Agarwal, André Ivanov, Dhiren Xavier:
A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes.
75-84
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- Oliver F. Haberl, Thomas Kropf:
HIST: A hierarchical self test methodology for chips, boards, and systems.
85-106
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- Fidel Muradali, Takao Nishida, Tsuguo Shimizu:
A structure and technique for pseudorandom-based testing of sequential circuits.
107-115
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- Soon Fatt Yoon:
Some observations from interrupted lifetest of GaInAsP/InP inverted-rib laser diodes.
117-125
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- Joan Figueras, Michel Renovell:
Current testing in dynamic CMOS circuits.
127-131
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- Maria J. Avedillo, José M. Quintana, José Luis Huertas:
Constrained state assignment of easily testable FSMs.
133-138
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- Slawomir Pilarski:
Comments on "Aliasing Properties of Circular MISRs".
139-140
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- Geetani Edirisooriya, John P. Robinson:
Authors' reply to comments on "Aliasing Properties of Circular MISRs".
141-142
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Volume 6,
Number 2,
April 1995
- Vishwani D. Agrawal:
Editorial.
147
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- William P. Marnane, W. R. Moore:
Testing VLSI regular arrays.
153-177
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- Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto:
Testability of artificial neural networks: A behavioral approach.
179-190
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- Manoj Sachdev:
Reducing the CMOS RAM test complexity withIDDQ and voltage testing.
191-202
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- Giacomo Buonanno, Franco Fummi, Donatella Sciuto:
TIES: A testability increase expert system for VLSI design.
203-217
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- Ilana David, Ran Ginosar, Michael Yoeli:
Self-timed is self-checking.
219-228
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- Dimitrios Kagaris, Spyros Tragoudas:
Avoiding linear dependencies in LFSR test pattern generators.
229-241
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- Shujian Zhang, Jon C. Muzio:
Evaluating the safety of self-checking circuits.
243-253
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- Kevin Cattell, Shujian Zhang:
Minimal cost one-dimensional linear hybrid cellular automata of degree through 500.
255-258
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Volume 6,
Number 3,
June 1995
Copyright © Sat May 16 23:58:50 2009
by Michael Ley (ley@uni-trier.de)
