ICCD 1991:
Cambridge,
MA,
USA
Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991.
IEEE Computer Society 1991, ISBN 0-8186-2270-9 BibTeX
@proceedings{DBLP:conf/iccd/1991,
title = {Proceedings 1991 IEEE International Conference on Computer Design:
VLSI in Computer {\&} Processors, ICCD '91, Cambridge, MA, USA,
October 14-16, 1991},
publisher = {IEEE Computer Society},
year = {1991},
isbn = {0-8186-2270-9},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynot Session
VLSI Plenary
Architecture Plenary
Design and Test Plenary
General Purpose Processors
- Yooichi Shintani, Kiyoshi Inoue, Toru Shonai, K. Wada, S. Abe, Katsuro Wakai:
Logic Design for a High Performance Mainframe Computer, The HITAC M-880 Processor.
14-20 BibTeX
- A. Shacham, Y. Levy, Z. Bronstein, E. Loewenstein, D. M. Bruck, D. Deitcher:
Architectural Considerations for SF-core Based Microprocessor.
21-24 BibTeX
Symbolic Layout and Module Generation
IWLS'91:
Combinational Optimization
Fault Simulation
IWLS'91:
Sequential Optimization
Simulation
Testing Regular Structures
High Performance VLSI Systems
- M. Hanawa, Tadahiko Nishimukai, O. Nishii, M. Suzuki, K. Yano, M. Hiraki, S. Shukuri, T. Nishida:
On-Chip Multiple Superscalar Processors with Secondary Cache Memories.
128-131 BibTeX
- Leith Johnson, Rob Horning, Larry Thayer, Daniel Li, Rob Snyder:
System Level ASIC Design for Hewleet-Packard's Low Cost PA-RISC Workstations.
132-135 BibTeX
- Moshe Shahaf:
DesignFab: A Methodology for ULSI Microprocessor Design.
136-139 BibTeX
- Maximo H. Salinas, Barry W. Johnson, James H. Aylor:
Implementation-Independent Model of an Instruction Set Architecture Using VHDL.
140-145 BibTeX
Panel Session
Monsoon
Routing Algorithms
Asynchronous Synthesis
Delay Testing
Large-Scale Multiprocessing
- Toshiyuki Tamura, Shinji Komori, Fumiyasu Asai, Hirono Tsubota, Hisakazu Sato, Hidehiro Takata, Yoshihiro Seguchi, Takeshi Tokuda, Hiroaki Terada:
A Data-Driven Architecture for Distributed Parallel Processing.
218-224 BibTeX
- Robert H. Payne, José G. Delgado-Frias:
MPU: A N-Tuple Matching Processor.
225-228 BibTeX
- Massimo Maresca, Pierpaolo Baglietto:
Transitive Closure and Graph Component Labeling on Realistic Processor Arrays Based on Reconfigurable Mesh Network.
229-232 BibTeX
- Hsin-Chou Chi, Yuval Tamir:
Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers.
233-238 BibTeX
Finite State Machine Verification
Built-In Self Test
High Speed Processor Technologies
- Craig Gleason, Mark Forsyth, Charlie Kohlhardt, Steve Mangelsdorf, Barry Arnold, Rick Luebs:
CMOS Processor Circuit Design in Hewlett-Packard's Series 700 Workstations.
288-292 BibTeX
- C. K. Tien, C. C. Poon, Hans J. Greub, Jack F. McDonald:
F-RISC/I: Fast Reduced Instruction Set Computer with GaAs (H)MESFET Implementation.
293-296 BibTeX
- K. Nah, Robert F. Philhower, J. S. Van Etten, S. Simmons, V. Tsinker, James Loy, Hans J. Greub, Jack F. McDonald:
F-RISC/G: AlGaAs/GaAs HBT Standard Cell Library.
297-300 BibTeX
- Peter R. Nuth, William J. Dally:
A Mechanism for Efficient Context Switching.
301-304 BibTeX
Floorplanning 1
MIPS
- Raymond Peck, Jay Patel:
Design Methodology for a MIPS Compatible Embedded Control Processor.
324-328 BibTeX
- Darren Jones, Rongken Yang, Mark Kwong, George Harper:
Verification Techniques for a MIPS Compatibvle Embedded Control Processor.
329-332 BibTeX
- Bob Culk, Sanjay Desai, Moshe Gavrielov, George Harper, Darren Jones, Mark Kwong, Marlon Murzello, Tim Oke, Jay Patel, Raymond Peck, James Wei, Rongken Yang:
The Architecture of the LR33000: A MIPS Compatible RISC Processor for Embedded Control Applications.
333-336 BibTeX
Formal Verification And Synthesis
Signature Analysis And Aliasing
Symbolic Processing
Performance Enhancement
High Level Synthesis
Redundancy Issues
ICCD Banquet
AS 400
Design And Test Automation
Interconnect And Packaging
Optical Computing
Special Purpose VLSI Architectures
- Shih-Fu Chang, David G. Messerschmitt:
VLSI Designs for High-Speed Huffman Decoder.
500-503 BibTeX
- C. Thomas White, Raj K. Singh, Peter B. Reintjes, Jordan Lampe, Bruce W. Erickson, Wayne D. Dettloff, Vernon L. Chi, Stephen F. Altschul:
BioSCAN: A VLSI-Based System for Biosequence Analysis.
504-509 BibTeX
- H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai:
VLSI Implementation of a New Block Cipher.
510-513 BibTeX
Floorplanning II
IBM ES/9000 VLSI
- Arnold E. Barish, James P. Eckhardt, Mark D. Mayo, Walter A. Svarczkopf, Santosh P. Gaur, Rao R. Tummala:
High Performance Packaged Electronics for the IBM ES9000TM Mainframe.
534-539 BibTeX
- W. J. Nohilly, V. T. Lund:
IBM ES/9000TM System Architecture and Hardware.
540-543 BibTeX
- R. S. Belanger, David P. Conrady, Philip S. Honsinger, T. J. Lavery, Sara J. Rothman, Erich C. Schanzenbach, D. Sitaram, C. R. Selinger, R. E. DuBois, G. W. Mahoney, G. F. Miceli:
Enhanced Chip/Package Design for the IBM ES/9000TM.
544-549 BibTeX
- Brion L. Keller, David A. Haynes:
Design Automation of Test for the EX/9000TM Series Processors.
550-553 BibTeX
Computer Arithmetic
Error Checking Schemes
Multichip Modules
- Robert F. Miracky, T. Bishop, Claire T. Galanakis, H. Hashemi, Tom J. Hirsch, S. Madere, Heinrich G. Müller, T. Rudwick, L. Smith, Scott C. Sommerfeldt, B. Weigler:
Technologies for Rapid Prototyping of Multi-Chip Modules.
588-592 BibTeX
- James B. Burr, Allen M. Peterson:
Energy Considerations in Multichip-Module Based Multiprocessors.
593-600 BibTeX
- Rudi Hendel:
The Commercial Realization of Multi-Chip Modules Quo Vadimus.
601-605 BibTeX
Numeric Processing
Random Thoughts In Logic Synthesis
Copyright © Sat May 16 23:16:39 2009
by Michael Ley (ley@uni-trier.de)
