Volume 20,
Number 1,
February 2004
- Vishwani D. Agrawal:
Editorial.
5-6
Electronic Edition (link) BibTeX
- A. Ivanov:
Test Technology Technical Council Newsletter.
7-8
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- Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski:
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations.
11-23
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- Viera Stopjaková, P. Malosek, D. Micusík, M. Matej, Martin Margala:
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks.
25-37
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- Chun-Lung Hsu:
Control and Observation Structure for Analog Circuits with Current Test Data.
39-44
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- Chih-Pin Su, Cheng-Wen Wu:
A Graph-Based Approach to Power-Constrained SOC Test Scheduling.
45-60
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- Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints.
61-78
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- Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda:
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
79-87
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- Kanad Chakraborty:
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.
89-108
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- Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa:
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.
109-122
Electronic Edition (link) BibTeX
Volume 20,
Number 2,
April 2004
- Vishwani D. Agrawal:
Editorial.
127
Electronic Edition (link) BibTeX
- P. Prinetto:
Test Technology Technical Council Newsletter.
131-132
Electronic Edition (link) BibTeX
- Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni:
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators.
133-142
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- Rosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras:
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.
143-153
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- Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin:
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.
155-168
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- Nicola Nicolici, Bashir M. Al-Hashimi:
Testability Trade-Offs for BIST Data Paths.
169-179
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- Ilia Polian, Bernd Becker:
Scalable Delay Fault BIST for Use with Low-Cost ATE.
181-197
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- Anshuman Chandra, Krishnendu Chakrabarty:
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes.
199-212
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- Amit M. Sheth, Jacob Savir:
Scan Latch Design for Test Applications.
213-216
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Volume 20,
Number 3,
June 2004
- Vishwani D. Agrawal:
Editorial.
219
Electronic Edition (link) BibTeX
- Paolo Prinetto:
Test Technology Technical Council Newsletter.
221-225
Electronic Edition (link) BibTeX
- Petru Cascaval, Stuart Bennett, Corneliu Hutanu:
Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories.
227-243
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- Said Hamdioui, Rob Wadsworth, John Delos Reyes, A. J. van de Goor:
Memory Fault Modeling Trends: A Case Study.
245-255
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- Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell:
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.
257-267
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- Fulvio Corno, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
Code Generation for Functional Validation of Pipelined Microprocessors.
269-278
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- Mehdi Baradaran Tahoori:
Application-Specific Bridging Fault Testing of FPGAs.
279-289
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- Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian:
Distributed Diagnosis of Interconnections in SoC and MCM Designs.
291-307
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- Sandeep Koranne:
A Note on System-on-Chip Test Scheduling Formulation.
309-313
Electronic Edition (link) BibTeX
- Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara:
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency.
315-323
Electronic Edition (link) BibTeX
Volume 20,
Number 4,
August 2004
Special Issue on the Third IEEE Latin-American Test Workshop
- Vishwani D. Agrawal:
Editorial.
327
Electronic Edition (link) BibTeX
- P. Prinetto:
Test Technology Technical Council Newsletter.
329
Electronic Edition (link) BibTeX
- Fabian Vargas, Víctor H. Champac:
Guest Editorial.
331-332
Electronic Edition (link) BibTeX
- J. C. Wang, Paulo Sérgio Cardoso, J. A. Q. Gonzalez, Marius Strum, R. Pires:
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data.
333-344
Electronic Edition (link) BibTeX
- Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, L. Balado, Joan Figueras:
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.
345-355
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- Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu:
Searching for Global Test Costs Optimization in Core-Based Systems.
357-373
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- Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.
375-387
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- Eduardo Romero, Gabriela Peretti, Carlos A. Marqués:
Oscillation Test Strategy: A Case Study.
389-396
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- Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum, Eduardo Luis Rhod:
Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems.
397-411
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- Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis:
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation.
413-421
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- Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell:
A New FPGA for DSP Applications Integrating BIST Capabilities.
423-431
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- Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
A New Approach to Software-Implemented Fault Tolerance.
433-437
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- Inali Wisniewski Soares, Silvia Regina Vergilio:
Mutation Analysis and Constraint-Based Criteria: Results from an Empirical Evaluation in the Context of Software Testing.
439-445
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- Luis Carlos Erpen De Bona, Elias Procópio Duarte Jr.:
A Flexible Approach for Defining Distributed Dependable Tests in SNMP-Based Network Management Systems.
447-454
Electronic Edition (link) BibTeX
Volume 20,
Number 5,
October 2004
On-line Testing
- Vishwani D. Agrawal:
Editorial.
459
Electronic Edition (link) BibTeX
- P. Prinetto:
Test Technology Technical Council Newsletter.
461-462
Electronic Edition (link) BibTeX
- Cecilia Metra, Matteo Sonza Reorda:
Guest Editorial.
463
Electronic Edition (link) BibTeX
- Steffen Tarnick:
Design of Embedded Self-Testing Checkers for t-UED and BUED Codes.
465-477
Electronic Edition (link) BibTeX
- Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
An Analog Checker with Input-Relative Tolerance for Duplicate Signals.
479-488
Electronic Edition (link) BibTeX
- Seok-Bum Ko, Jien-Chung Lo:
Efficient Realization of Parity Prediction Functions in FPGAs.
489-499
Electronic Edition (link) BibTeX
- Martin Omaña, Daniele Rossi, Cecilia Metra:
Model for Transient Fault Susceptibility of Combinational Circuits.
501-509
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- Matteo Sonza Reorda, Massimo Violante:
A New Approach to the Analysis of Single Event Transients in VLSI Circuits.
511-521
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- Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs.
523-531
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- André K. Nieuwland, Richard P. Kleihorst:
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors.
533-542
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- B. Alorda, Vincent Canals, Jaume Segura:
A Two-Level Power-Grid Model for Transient Current Testing Evaluation.
543-552
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- Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour:
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features.
553-567
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Volume 20,
Number 6,
December 2004
- Vishwani D. Agrawal:
Editorial.
571
Electronic Edition (link) BibTeX
- Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi:
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
575-589
Electronic Edition (link) BibTeX
- Soumitra Bose:
Modeling Custom Digital Circuits for Test.
591-609
Electronic Edition (link) BibTeX
- Michael Gössel, Krishnendu Chakrabarty, Vitalij Ocheretnij, Andreas Leininger:
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST.
611-622
Electronic Edition (link) BibTeX
- Sunil Rafeeque, Vinita Vasudevan:
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.
623-638
Electronic Edition (link) BibTeX
- Octavian Petre, Hans G. Kerkhoff:
Scan Test Strategy for Asynchronous-Synchronous Interfaces.
639-645
Electronic Edition (link) BibTeX
- Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
Power-Driven Routing-Constrained Scan Chain Design.
647-660
Electronic Edition (link) BibTeX
- Seok-Bum Ko:
Area Minimization of Exclusive-OR Intensive Circuits in FPGAs.
661-665
Electronic Edition (link) BibTeX
- Lei Li, Krishnendu Chakrabarty:
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression.
667-670
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:58:52 2009
by Michael Ley (ley@uni-trier.de)
