Volume 28,
Number 1,
January 1979
Correspondence
- Vinod K. Agarwal, Gerald M. Masson:
A Functional Form Approach to Test Set Coverage in Tree Networks.
50-52 BibTeX
- Y. Zisapel, M. Krieger, J. Kella:
Detection of Hazards in Combinational Switching Circuits.
52-56 BibTeX
- H. J. Trussel, Bobby R. Hunt:
Improved Methods of Maximum a Posteriori Restoration.
57-62 BibTeX
- Brian R. Gaines:
Maryanski's Grammatical Inferencer.
62-64 BibTeX
- Fred J. Maryanski, Taylor L. Booth:
Authors' Reply.
64 BibTeX
- Erkki Oja:
On the Construction of Projectors Using Products of Elementary Matrices.
65-66 BibTeX
- Tsutomu Sasao, Kozo Kinoshita:
On the Number of Fanout-Free Functions and Unate Cascade Functions.
66-72 BibTeX
- Mordechai Ben-Ari:
On Transposing Large 2n × 2n Matrices.
72-75 BibTeX
- Jay Niel Culliney, Ming Huei Young, T. Nakagawa, Saburo Muroga:
Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions.
76-85 BibTeX
- R. David, R. Tellez-Giron:
Comments on ``The Error Latency of a Fault in a Sequential Digital Circuit''.
85-86 BibTeX
Volume 28,
Number 2,
February 1979
Correspondence
Volume 28,
Number 3,
March 1979
Correspondence
Volume 28,
Number 4,
April 1979
Correspondence
Volume 28,
Number 5,
May 1979
Correspondence
Volume 28,
Number 6,
June 1979
Volume 28,
Number 7,
July 1979
Correspondence
Volume 28,
Number 8,
August 1979
Correspondence
Volume 28,
Number 9,
September 1979
- Suhas S. Patil, Terry A. Welch:
A Programmable Logic Approach for VLSI.
594-601 BibTeX
- Roy A. Wood:
A High Density Programmable Logic Array Chip.
602-608 BibTeX
- Yahiko Kambayashi:
Logic Design of Programmable Logic Arrays.
609-617 BibTeX
- Daniel L. Ostapko, Se June Hong:
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's).
617-627 BibTeX
- Share Young Lee, Hsu Chang:
Associative-Search Bubble Devices for Content-Addressable Memory and Array Logic.
627-636 BibTeX
- Heinrich Pangratz, Hans Weinrichter:
Pseudo-Random Number Generator Based on Binary and Quinary Maximal-Length Sequences.
637-642 BibTeX
- Jon Louis Bentley, Thomas Ottmann:
Algorithms for Reporting and Counting Geometric Intersections.
643-647 BibTeX
- Hung Chi Lai, Saburo Muroga:
Minimum Parallel Binary Adders with NOR (NAND) Gates.
648-659 BibTeX
- Utpal Banerjee, Shyh-Ching Chen, David J. Kuck, Ross A. Towle:
Time and Parallel Processor Bounds for Fortran-Like Loops.
660-670 BibTeX
- Joseph Y.-T. Leung, Edmund K. Lai:
On Minimum Cost Recovery from System Deadlock.
671-677 BibTeX
- B. Ramakrishna Rau:
Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System.
678-681 BibTeX
Correspondence
Volume 28,
Number 10,
October 1979
- Andrew Hopper, David J. Wheeler:
Binary Routing Networks.
609-703 BibTeX
- Steven I. Kartashev, Svetlana P. Kartashev:
A Multicomputer System with Dynamic Architecture.
704-721 BibTeX
- I-Ngo Chen, Robert Willoner:
An 0(n) Parallel Multiplier with Bit-Sequential Input and Output.
721-727 BibTeX
- Yasuhito Suenaga, Takahiko Kamae, Tomonori Kobayashi:
A High-Speed Algorithm for the Generation of Straight Lines and Circular Arcs.
728-736 BibTeX
- Erol Gelenbe, Kenneth C. Sevcik:
Analysis of Update Synchronization for Multiple Copy Data Bases.
737-747 BibTeX
- John B. Kam, George I. Davida:
Structured Design of Substitution-Permutation Encryption Networks.
747-753 BibTeX
- Charles R. Kime:
An Abstract Model for Digital System Fault Diagnosis.
754-767 BibTeX
- Keijiro Nakamura:
Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks.
768-772 BibTeX
- Edmund A. Lamagna:
The Complexity of Monotone Networks for Certain Bilinear Forms, Routing Problems, Sorting, and Merging.
773-782 BibTeX
- Teofilo F. Gonzalez:
A Note on Open Shop Preemptive Schedules.
782-786 BibTeX
Correspondence
Volume 28,
Number 11,
November 1979
Correspondence
Volume 28,
Number 12,
December 1979
Correspondence
Copyright © Sun May 17 00:22:57 2009
by Michael Ley (ley@uni-trier.de)
