Volume 21,
Number 1,
February 2005
- Vishwani D. Agrawal:
Editorial.
5
Electronic Edition (link) BibTeX
- Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell:
A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters.
9-16
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- Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen:
Optimal Interconnect ATPG Under a Ground-Bounce Constraint.
17-31
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- Jean Michel Portal, H. Aziza, Didier Née:
EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement.
33-42
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- Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.
43-55
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- Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker:
Modeling Feedback Bridging Faults with Non-Zero Resistance.
57-69
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- Jaan Raik, Tanel Nõmmeots, Raimund Ubar:
A New Testability Calculation Method to Guide RTL Test Generation.
71-82
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- Biplab K. Sikdar, Samir Roy, Debesh K. Das:
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area.
83-93
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- Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time.
95-107
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Volume 21,
Number 2,
April 2005
- Vishwani D. Agrawal:
Editorial.
111
Electronic Edition (link) BibTeX
- Bruce C. Kim:
Test Technology Technical Council Newsletter.
113-114
Electronic Edition (link) BibTeX
- Anand L. D'Souza, Michael S. Hsiao:
Error Diagnosis of Sequential Circuits Using Region-Based Model.
115-126
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- Yvan Maidon, Thomas Zimmer, André Ivanov:
An Analog Circuit Fault Characterization Methodology.
127-134
Electronic Edition (link) BibTeX
- Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell:
Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks.
135-146
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- Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
147-159
Electronic Edition (link) BibTeX
- Dimitri Kagaris:
Phase Shifter Merging.
161-168
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- Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.
169-179
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- Huawei Li, Xiaowei Li:
Selection of Crosstalk-Induced Faults in Enhanced Delay Test.
181-195
Electronic Edition (link) BibTeX
Volume 21,
Number 3,
June 2005
- Vishwani D. Agrawal:
Editorial.
199
Electronic Edition (link) BibTeX
- Bruce C. Kim:
Test Technology Technical Council Newsletter.
201
Electronic Edition (link) BibTeX
- Adoración Rueda, Michel Renovell, José Luis Huertas:
Guest Editorial.
203
Electronic Edition (link) BibTeX
- Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio:
An On-Chip Spectrum Analyzer for Analog Built-In Testing.
205-219
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- Diego Vázquez, Gloria Huertas, África Luque, Manuel J. Barragan Asian, Gildas Leger, Adoración Rueda, José Luis Huertas:
Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST.
221-232
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- Libor Rufer, Salvador Mir, Emmanuel Simeu, C. Domingues:
On-Chip Pseudorandom MEMS Testing.
233-241
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- Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy:
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
243-255
Electronic Edition (link) BibTeX
- R. Sanahuja, V. Barcons, L. Balado, Joan Figueras:
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning.
257-265
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- Martin John Burbidge:
Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods.
267-281
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- Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin, Felipe R. Clayton, Cristiano Benevento:
Low Cost BIST for Static and Dynamic Testing of ADCs.
283-290
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- Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell:
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.
291-298
Electronic Edition (link) BibTeX
- Carsten Wegener, Michael Peter Kennedy:
Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs.
299-310
Electronic Edition (link) BibTeX
- José Pineda de Gyvez, Guido Gronthoud, Rashid Amine:
Multi-VDD Testing for Analog Circuits.
311-322
Electronic Edition (link) BibTeX
- Soumendu Bhattacharya, Achintya Halder, Ganesh Srinivasan, Abhijit Chatterjee:
Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications.
323-339
Electronic Edition (link) BibTeX
Volume 21,
Number 4,
August 2005
Special Issue on On-Line-Testing and Fault Tolerance
- D. Barros Júnior, M. Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, João Paulo Teixeira:
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip.
349-363
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- Abdelaziz Ammari, K. Hadjiat, Régis Leveugle:
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation.
365-376
Electronic Edition (link) BibTeX
- José Manuel Cazeaux, Daniele Rossi, Cecilia Metra:
Self-Checking Voter for High Speed TMR Systems.
377-389
Electronic Edition (link) BibTeX
- Steffen Tarnick:
Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes.
391-404
Electronic Edition (link) BibTeX
- Carl Jeffrey, Reuben Cutajar, Andrew Richardson, Stephen Prosser, M. Lickess, Stephen Riches:
The Integration of On-Line Monitoring and Reconfiguration Functions into a Safety Critical Automotive Electronic Control Unit.
405-416
Electronic Edition (link) BibTeX
- Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
Low Cost On-Line Testing Strategy for RF Circuits.
417-427
Electronic Edition (link) BibTeX
- Gian-Carlo Cardarilli, Fabrizio Lombardi, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A Comparative Evaluation of Designs for Reliable Memory Systems.
429-444
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- Michael Nicolaidis, Lorena Anghel, Nadir Achouri:
Memory Defect Tolerance Architectures for Nanotechnologies.
445-455
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Volume 21,
Number 5,
October 2005
- Vishwani D. Agrawal:
Editorial.
459
Electronic Edition (link) BibTeX
- Bruce C. Kim:
The Newsletter of Test Technology Council of the IEEE Computer Society.
461-462
Electronic Edition (link) BibTeX
- Chintan Patel, Abhishek Singh, Jim Plusquellic:
Defect Detection Using Quiescent Signal Analysis.
463-483
Electronic Edition (link) BibTeX
- Andreas G. Veneris, Jiang Brandon Liu:
Incremental Design Debugging in a Logic Synthesis Environment.
485-494
Electronic Edition (link) BibTeX
- Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi:
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.
495-502
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- Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra:
A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation.
503-537
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- Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin:
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m).
539-549
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- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.
551-561
Electronic Edition (link) BibTeX
Volume 21,
Number 6,
December 2005
- Vishwani D. Agrawal:
Editorial.
567
Electronic Edition (link) BibTeX
- Jee-Youl Ryu, Bruce C. Kim:
Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit.
571-581
Electronic Edition (link) BibTeX
- Y. Lechuga, R. Mozuelos, M. A. Allende, Mar Martínez, Salvador Bracho:
Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors.
583-598
Electronic Edition (link) BibTeX
- Julien Pouget, Erik Larsson, Zebo Peng:
Multiple-Constraint Driven System-on-Chip Test Time Optimization.
599-611
Electronic Edition (link) BibTeX
- Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita:
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.
613-620
Electronic Edition (link) BibTeX
- Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei:
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.
621-630
Electronic Edition (link) BibTeX
- Joonhwan Yi, John P. Hayes:
The Coupling Model for Function and Delay Faults.
631-649
Electronic Edition (link) BibTeX
- Erik Larsson, Julien Pouget, Zebo Peng:
Abort-on-Fail Based Test Scheduling.
651-658
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:58:52 2009
by Michael Ley (ley@uni-trier.de)
