2009 |
18 | EE | Lavanya Jagan,
Ratan Deep Singh,
V. Kamakoti,
Ananta K. Majhi:
Efficient Grouping of Fail Chips for Volume Yield Diagnostics.
VLSI Design 2009: 97-102 |
2007 |
17 | EE | Daniel Arumí,
Rosa Rodríguez-Montañés,
Joan Figueras,
Stefan Eichenberger,
Camelia Hora,
Bram Kruseman,
Maurice Lousberg,
Ananta K. Majhi:
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.
VTS 2007: 145-150 |
16 | EE | Rosa Rodríguez-Montañés,
Daniel Arumí,
Joan Figueras,
Stefan Eichenberger,
Camelia Hora,
Bram Kruseman,
Maurice Lousberg,
Ananta K. Majhi:
Diagnosis of Full Open Defects in Interconnecting Lines.
VTS 2007: 158-166 |
15 | EE | Bram Kruseman,
Ananta K. Majhi,
Guido Gronthoud:
On Performance Testing with Path Delay Patterns.
VTS 2007: 29-34 |
14 | EE | Ananta K. Majhi,
Mohamed Azimane,
Guido Gronthoud,
Maurice Lousberg,
Stefan Eichenberger,
Fred Bowen:
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
CoRR abs/0710.4693: (2007) |
13 | EE | Jing Wang,
Duncan M. Hank Walker,
Xiang Lu,
Ananta K. Majhi,
Bram Kruseman,
Guido Gronthoud,
Luis Elvira Villagra,
Paul J. A. M. van de Wiel,
Stefan Eichenberger:
Modeling Power Supply Noise in Delay Testing.
IEEE Design & Test of Computers 24(3): 226-234 (2007) |
2005 |
12 | EE | Ananta K. Majhi,
Mohamed Azimane,
Guido Gronthoud,
Maurice Lousberg,
Stefan Eichenberger,
Fred Bowen:
Memory Testing Under Different Stress Conditions: An Industrial Evaluation.
DATE 2005: 438-443 |
11 | EE | Mohamed Azimane,
Ananta K. Majhi,
Guido Gronthoud,
Maurice Lousberg:
A New Algorithm for Dynamic Faults Detection in RAMs.
VTS 2005: 177-182 |
2004 |
10 | EE | Bram Kruseman,
Ananta K. Majhi,
Guido Gronthoud,
Stefan Eichenberger:
On Hazard-free Patterns for Fine-delay Fault Testing.
ITC 2004: 213-222 |
9 | EE | Bram Kruseman,
Ananta K. Majhi,
Camelia Hora,
Stefan Eichenberger,
Johan Meirlevede:
Systematic Defects in Deep Sub-Micron Technologies.
ITC 2004: 290-299 |
8 | EE | Mohamed Azimane,
Ananta K. Majhi:
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders.
VTS 2004: 123-128 |
2003 |
7 | EE | Ananta K. Majhi,
Guido Gronthoud,
Camelia Hora,
Maurice Lousberg,
Pop Valer,
Stefan Eichenberger:
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.
VTS 2003: 345-350 |
2000 |
6 | EE | Ananta K. Majhi,
V. D. Agrawak,
James Jacob,
Lalit M. Patnaik:
Line coverage of path delay faults.
IEEE Trans. VLSI Syst. 8(5): 610-614 (2000) |
1998 |
5 | EE | Ananta K. Majhi,
Vishwani D. Agrawal:
Mixed-Signal Test.
VLSI Design 1998: 285-288 |
4 | EE | Ananta K. Majhi,
Vishwani D. Agrawal:
Tutorial: Delay Fault Models and Coverage.
VLSI Design 1998: 364-369 |
3 | EE | S. Balajee,
Ananta K. Majhi:
Automated AC (Timing) Characterization for Digital Circuit Testing.
VLSI Design 1998: 374-377 |
1996 |
2 | EE | Ananta K. Majhi,
James Jacob,
Lalit M. Patnaik,
Vishwani D. Agrawal:
On test coverage of path delay faults.
VLSI Design 1996: 418-421 |
1995 |
1 | EE | Ananta K. Majhi,
James Jacob,
Lalit M. Patnaik,
Vishwani D. Agrawal:
An efficient automatic test generation system for path delay faults in combinational circuits.
VLSI Design 1995: 161-165 |