| 2006 |
|---|
| 7 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
Transistor Sizing of Logic Gates to Maximize Input Delay Variability.
J. Low Power Electronics 2(1): 121-128 (2006) |
| 2005 |
|---|
| 6 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
Design of Variable Input Delay Gates for Low Dynamic Power Circuits.
PATMOS 2005: 436-445 |
| 5 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
Variable Input Delay CMOS Logic for Low Power Design.
VLSI Design 2005: 598-605 |
| 2004 |
|---|
| 4 | EE | Tezaswi Raja,
Manish Parashar:
Using a Jini based desktop Grid for test vector compaction and a refined economic model.
CCGRID 2004: 798-805 |
| 3 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.
VLSI Design 2004: 1035-1040 |
| 2 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
A Tuturial on the Emerging Nanotechnology Devices.
VLSI Design 2004: 343-360 |
| 2003 |
|---|
| 1 | EE | Tezaswi Raja,
Vishwani D. Agrawal,
Michael L. Bushnell:
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.
VLSI Design 2003: 527-532 |
