Journal of Electronic Testing, Volume 18

Volume 18, Number 1, February 2002

• Vishwani D. Agrawal:
  Editorial. 5
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• Kozo Kinoshita:
  Foreword. 13
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• Kuen-Jong Lee, Chau-chin Su:
  Guest Editorial. 15-16
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• Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
  Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. 17-28
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• Yiorgos Makris, Jamison Collins, Alex Orailoglu:
  Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface. 29-42
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• Wei-Lun Wang, Kuen-Jong Lee:
  An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. 43-53
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• Michiko Inoue, Emil Gizdarski, Hideo Fujiwara:
  Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. 55-62
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• Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
  State and Fault Information for Compaction-Based Test Generation. 63-72
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• Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
  TA-PSV - Timing Analysis for Partially Specified Vectors. 73-88
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• Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen:
  Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. 89-97
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Volume 18, Number 2, April 2002

• Vishwani D. Agrawal:
  Editorial. 103-104
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• André Ivanov:
  Test Technology Technical Council Newsletter. 105-106
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• Christian Landrault:
  Guest Editorial. 107
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• Yukiya Miura, Shuichi Seno:
  Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits. 109-120
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• Daniela De Venuto, Michael J. Ohletz, Bruno Riccò:
  Digital Window Comparator DfT Scheme for Mixed-Signal ICs. 121-128
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• Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier:
  Enhanced Reduced Pin-Count Test for Full-Scan Design. 129-143
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• René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
  Hardware Generation of Random Single Input Change Test Sequences. 145-157
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• Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:
  Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. 159-170
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• Magnus Eckersand, Fredrik Franzon, Ken Filliter:
  Using At-Speed BIST to Test LVDS Serializer/Deserializer Function. 171-177
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• Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
  RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. 179-187
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• Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy:
  Synthesis of Scan Chains for Netlist Descriptions at RT-Level. 189-201
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• V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff:
  An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures. 203-212
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• Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. 213-230
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• Rainer Dorsch, Hans-Joachim Wunderlich:
  Reusing Scan Chains for Test Pattern Decompression. 231-240
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• Maisaa Khalil, Chantal Robach, Franc Novak:
  Diagnosis Strategies for Hardware or Software Systems. 241-251
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Volume 18, Number 3, June 2002

• Vishwani D. Agrawal:
  Editorial. 255
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• André Ivanov:
  Test Technology Technical Council Newsletter. 257-258
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• Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra:
  Guest Editorial. 259-260
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• Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
  An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. 261-271
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• Michele Favalli, Cecilia Metra:
  Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. 273-283
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• Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
  Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. 285-294
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• Ashish Syal, Victor Lee, André Ivanov, Josep Altet:
  CMOS Differential and Absolute Thermal Sensors. 295-304
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• Dimitrios Kagaris, Spyros Tragoudas:
  Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. 305-313
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• Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
  On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. 315-332
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• Cristoforo Marzocca, Francesco Corsi:
  Mixed-Signal Circuit Classification in a Pseudo-Random Testing Scheme. 333-342
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• Joakim Aidemark, Peter Folkesson, Johan Karlsson:
  Path-Based Error Coverage Prediction. 343-349
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• Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto:
  Reliability Properties Assessment at System Level: A Co-Design Framework. 351-356
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Volume 18, Numbers 4-5, August 2002

• Vishwani D. Agrawal:
  Editorial. 359
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• André Ivanov:
  Test Technology Technical Council Newsletter. 361-362
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• Krishnendu Chakrabarty:
  Guest Editorial. 363
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• Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian:
  On IEEE P1500's Standard for Embedded Core Test. 365-383
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• Erik Larsson, Zebo Peng:
  An Integrated Framework for the Design and Optimization of SOC Test Solutions. 385-400
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• Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy:
  On Concurrent Test of Core-Based SOC Design. 401-414
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• Sandeep Koranne:
  A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm. 415-434
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• Erik Jan Marinissen:
  The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. 435-454
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• Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki:
  CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. 455-473
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• Subhayu Basu, Indranil Sengupta, Dipanwita Roy Chowdhury, Sudipta Bhawmik:
  An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch. 475-485
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• Tomokazu Yoneda, Hideo Fujiwara:
  Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. 487-501
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• Abhijit Jas, Nur A. Touba:
  Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. 503-514
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• Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu:
  Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. 515-527
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• Li Chen, Xiaoliang Bai, Sujit Dey:
  Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. 529-538
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• Mehrdad Nourani, Amir Attarha:
  Signal Integrity: Fault Modeling and Testing in High-Speed SoCs. 539-554
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• Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò:
  On-Chip Clock Faults' Detector. 555-564
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Volume 18, Number 6, December 2002

• Vishwani D. Agrawal:
  Editorial. 567-568
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• Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
  Structural Fault Based Specification Reduction for Testing Analog Circuits. 571-581
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• Tom Chen, Andre Bai, Amjad Hajjar, Anneliese Amschler Andrews, Charles Anderson:
  Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification. 583-594
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• Sandhya Seshadri, Michael S. Hsiao:
  Behavioral-Level DFT via Formal Operator Testability Measures. 595-611
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• Bruce S. Greene, Samiha Mourad:
  Partial Scan Testing on the Register-Transfer Level. 613-626
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• Kuen-Jong Lee, Tsung-Chu Huang:
  An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. 627-636
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• Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
  A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. 637-647
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