IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 5

Volume 5, Number 1, March 1997

• Stuart K. Tewksbury, Glenn H. Chapman:
  Guest Editorial Foreword to the Special Section on WSI'95. 1-2
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• Zahava Koren, Israel Koren:
  On the effect of floorplanning on the yield of large area integrated circuits. 3-14
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• Vijay K. Jain, Lei Lin:
  Complex-argument universal nonlinear cell for rapid prototyping. 15-27
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• Yves Audet, Glenn H. Chapman:
  Yield improvement of a large area magnetic field sensor array using redundancy schemes. 28-33
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• Shantanu Dutt, Fran Hanchek:
  REMOD: a new methodology for designing fault-tolerant arithmetic circuits. 34-56
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• Ahmed Amine Jerraya, Gert Goossens:
  Guest Editorial Introduction to the Special Issue on the Eighth IEEE International Symposium on System Synthesis. 57-58
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• Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man:
  Synthesis of pipelined DSP accelerators with dynamic scheduling. 59-68
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• Samit Chaudhuri, S. A. Blthye, Robert A. Walker:
  A solution methodology for exact design space exploration in a three-dimensional design space. 69-81
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• Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan:
  Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. 82-100
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• Herman Schmit, Donald E. Thomas:
  Synthesis of application-specific memory designs. 101-111
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• Rainer Leupers, Peter Marwedel:
  Time-constrained code compaction for DSPs. 112-122
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• Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita:
  Power analysis and minimization techniques for embedded DSP software. 123-135
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• Jean-Marc Daveau, Gilberto Fernandes Marchioro, Tarek Ben Ismail, Ahmed Amine Jerraya:
  Protocol selection and interface generation for HW-SW codesign. 136-144
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• Luigi Raffo, Silvio P. Sabatini, M. Mantelli, A. De Gloria, Giacomo M. Bisio:
  Design of an ASIP architecture for low-level visual elaborations. 145-153
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Volume 5, Number 2, June 1997

• Mohamed Nekili, Guy Bois, Yvon Savaria:
  Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. 161-174
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• Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal:
  Scheduling tests for VLSI systems under power constraints. 175-185
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• Yen-Tai Lai, Ping-Tsung Wang:
  Hierarchical interconnection structures for field programmable gate arrays. 186-196
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• Steve C.-Y. Huang, Wayne Wolf:
  Unifiable scheduling and allocation for minimizing system cycle time. 197-210
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• Yongjin Jeong, Wayne P. Burleson:
  VLSI array algorithms and architectures for RSA modular multiplication. 211-217
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• W. H. Wolf:
  An architectural co-synthesis algorithm for distributed, embedded computing systems. 218-229
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• David Zhang, Mohamed I. Elmasry:
  VLSI compressor design with applications to digital neural networks. 230-233
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• Pi-Yu Chung, Ibrahim N. Hajj:
  Diagnosis and correction of multiple logic design errors in digital circuits. 233-237
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• C.-K. V. Tien, K. Lewis, Hans J. Greub, T. Tsen, John F. McDonald:
  Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology. 238-243
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Volume 5, Number 3, September 1997

• G. Digele, S. Lindenkreuz, E. Kasper:
  Fully coupled dynamic electro-thermal simulation. 250-257
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• Vladimir Székely, András Poppe, A. Pahi, A. Csendes, G. Hajas, Márta Rencz:
  Electro-thermal and logi-thermal simulation of VLSI designs. 258-269
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• Vladimir Székely, C. Marta, Z. Kohari, Márta Rencz:
  CMOS sensors for on-line thermal monitoring of VLSI circuits. 270-276
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• S. Wünsche, C. Clauss, P. Schwarz, Frank Winkler:
  Electro-thermal circuit simulation using simulator coupling. 277-282
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• M.-N. Sabry, A. Bontemps, V. Aubert, R. Vahrmann:
  Realistic and efficient simulation of electro-thermal effects in VLSI circuits. 283-289
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• S. R. Vemuru:
  Effects of simultaneous switching noise on the tapered buffer design. 290-300
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• Hiok-Tiaq Ng, David J. Allstot:
  CMOS current steering logic for low-voltage mixed-signal integrated circuits. 301-308
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• Yong Je Lim, Mani Soma:
  Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits. 309-319
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• A. Lipman, W. Yang:
  VLSI hardware for example-based learning. 320-328
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• A. Bugeja, W. Yang:
  A reconfigurable VLSI coprocessing system for the block matching algorithm. 329-337
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• Kamal Kantawala, D. L. Tao:
  Design, analysis, and evaluation of concurrent checking sorting networks. 338-343
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Volume 5, Number 4, December 1997

• Jun Ma, Han-Bin Liang, R. A. Pryor, Sunny Cheng, M. H. Kaneshiro, C. S. Kyono, Ken Papworth:
  Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications. 352-359
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• M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf:
  The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. 360-368
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• Xinghai Tang, Vivek De, James D. Meindl:
  Intrinsic MOSFET parameter fluctuations due to random dopant placement. 369-376
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• Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa:
  A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. 377-387
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• Ram K. Krishnamurthy, L. Richard Carley:
  Exploring the design space of mixed swing quadrail for low-power digital circuits. 388-400
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• Godi Fischer, James C. Daly, Conrad W. Recksiek, Kevin D. Friedland:
  A programmable temperature monitoring device for tagging small fish: a prototype chip development. 401-407
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• Qiuting Huang, Philipp Basedau:
  Design considerations for high-frequency crystal oscillators digitally trimmable to sub-ppm accuracy. 408-416
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• Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki:
  Instruction buffering to reduce power in processors for signal processing. 417-424
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• Vadim Gutnik, Anantha P. Chandrakasan:
  Embedded power supply for low-power DSP. 425-435
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• Jui-Ming Chang, Massoud Pedram:
  Energy minimization using multiple supply voltages. 436-443
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• Mircea R. Stan, Wayne P. Burleson:
  Low-power encodings for global communication in CMOS VLSI. 444-455
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• A. Tuagi:
  Entropic bounds on FSM switching. 456-464
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• Olivier Coudert:
  Gate sizing for constrained delay/power/area optimization. 465-472
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• Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò:
  Gate-level power and current simulation of CMOS integrated circuits. 473-488
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