| 2001 |
|---|
| 8 | EE | Jane Cleland-Huang,
Carl K. Chang,
Hosung Kim,
Arun Balakrishnan:
Requirements-Based Dynamic Metrics In Object-Oriented Systems.
RE 2001: 212-221 |
| 1998 |
|---|
| 7 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Peripheral Partitioning and Tree Decomposition for Partial Scan.
VLSI Design 1998: 181-186 |
| 1996 |
|---|
| 6 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Sequential Circuits with combinational Test Generation Complexity.
VLSI Design 1996: 111-117 |
| 5 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Retiming with logic duplication transformation: theory and an application to partial scan.
VLSI Design 1996: 296-302 |
| 1995 |
|---|
| 4 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Software transformations for sequential test generation.
Asian Test Symposium 1995: 266- |
| 3 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Partial scan design for technology mapped circuits.
VLSI Design 1995: 283-287 |
| 2 | EE | Srimat T. Chakradhar,
Arun Balakrishnan,
Vishwani D. Agrawal:
An exact algorithm for selecting partial scan flip-flops.
J. Electronic Testing 7(1-2): 83-93 (1995) |
| 1994 |
|---|
| 1 | EE | Srimat T. Chakradhar,
Arun Balakrishnan,
Vishwani D. Agrawal:
An Exact Algorithm for Selecting Partial Scan Flip-Flops.
DAC 1994: 81-86 |
