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Yuanlin Lu

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2008
4EEYuanlin Lu, Vishwani D. Agrawal: Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. VLSI Design 2008: 527-532
2007
3EEYuanlin Lu, Vishwani D. Agrawal: Statistical Leakage and Timing Optimization for Submicron Process Variation. VLSI Design 2007: 439-444
2006
2EEYuanlin Lu, Vishwani D. Agrawal: CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. J. Low Power Electronics 2(3): 378-387 (2006)
2005
1EEYuanlin Lu, Vishwani D. Agrawal: Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. PATMOS 2005: 217-226

Coauthor Index

1Vishwani D. Agrawal [1] [2] [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)