2008 | ||
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4 | EE | Yuanlin Lu, Vishwani D. Agrawal: Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. VLSI Design 2008: 527-532 |
2007 | ||
3 | EE | Yuanlin Lu, Vishwani D. Agrawal: Statistical Leakage and Timing Optimization for Submicron Process Variation. VLSI Design 2007: 439-444 |
2006 | ||
2 | EE | Yuanlin Lu, Vishwani D. Agrawal: CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. J. Low Power Electronics 2(3): 378-387 (2006) |
2005 | ||
1 | EE | Yuanlin Lu, Vishwani D. Agrawal: Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. PATMOS 2005: 217-226 |
1 | Vishwani D. Agrawal | [1] [2] [3] [4] |