Journal of Electronic Testing, Volume 8

Volume 8, Number 1, February 1996

• Xinghao Chen, Michael L. Bushnell:
  Sequential circuit test generation using dynamic justification equivalence. 9-33
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• Rosa Rodríguez-Montañés, E. M. J. G. Bruls, Joan Figueras:
  Bridging defects resistance in the metal layer of a CMOS process. 35-46
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• Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges:
  Statistical estimation of delay fault detectabilities and fault grading. 47-60
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• David Wessels, Jon C. Muzio:
  The dangers of simplistic delay models. 61-69
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• Krishnendu Chakrabarty, John P. Hayes:
  Balance testing and balance-testable design of logic circuits. 71-86
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• Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman:
  Diagnostic simulation of stuck-at faults in combinational circuits. 87-97
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Volume 8, Number 2, April 1996

• Vishwani D. Agrawal:
  Editorial. 111
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• Ayman M. Wahba, Dominique Borrione:
  A method for automatic design error location and correction in combinational logic circuits. 113-127
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• Janusz A. Brzozowski, Helmut Jürgensen:
  An algebra of multiple faults in RAMs. 129-142
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• Pascal Caunegre, Claude Abraham:
  Fault simulation for mixed-signal systems. 143-152
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• Samir Boubezari, Bozena Kaminska:
  A new reconfigurable Test Vector Generator for built-in self-test applications. 153-164
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• Michael Gössel, Egor S. Sogomonyan:
  A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST. 165-177
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• Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
  Monitoring machine based synthesis technique for concurrent error detection in finite state machines. 179-201
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• Manoj Sachdev:
  SeparateI_DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis. 203-214
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• Kanji Hirabayashi:
  Hazard simulation of sequential circuits. 215-217
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• Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis:
  An efficient built-in self test method for robust path delay fault testing. 219-222
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Volume 8, Number 3, June 1996

• Jaume Segura, C. Benito, A. Rubio, Charles F. Hawkins:
  A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. 229-239
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• Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis:
  C-Testable modified-Booth multipliers. 241-260
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• Niranjan L. Cooray, Edward W. Czeck:
  Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation. 261-273
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• Sreejit Chakravarty, Paul J. Thadikaran:
  Algorithms to select I_DDQ measurement points to detect bridging faults. 275-285
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• Michael G. McNamer, H. Troy Nagle:
  ITA: An algorithm for I_DDQ testability analysis. 287-298
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