| 1995 |
|---|
| 6 | EE | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A partition and resynthesis approach to testable design of large circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1268-1276 (1995) |
| 5 | EE | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
Test function embedding algorithms with application to interconnected finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1115-1127 (1995) |
| 1994 |
|---|
| 4 | | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A Test Function Architecture for Interconnected Finite State Machines.
VLSI Design 1994: 113-116 |
| 1993 |
|---|
| 3 | | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A Synthesis Approach to Design for Testability.
ITC 1993: 754-763 |
| 2 | EE | Srimat T. Chakradhar,
Suman Kanjilal,
Vishwani D. Agrawal:
Finite state machine synthesis with fault tolerant test function.
J. Electronic Testing 4(1): 57-69 (1993) |
| 1992 |
|---|
| 1 | EE | Srimat T. Chakradhar,
Suman Kanjilal,
Vishwani D. Agrawal:
Finite State Machine Synthesis with Fault Tolerant Test Function.
DAC 1992: 562-567 |
