Journal of Electronic Testing, Volume 17

Volume 17, Number 1, February 2001

• Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal:
  SIVA: A System for Coverage-Directed State Space Search. 11-27
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• Farzan Aminian, Mehran Aminian:
  Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor. 29-36
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• Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
  Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. 37-51
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• Iboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska:
  A Unity Gain High Speed Buffer to Improve Signal Integrity in High Frequency Test Interface. 53-61
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• Cher Ming Tan, Kelvin Ngan Chong Yeo:
  A Reliability Statistics Perspective on the Pitfalls of Standard Wafer-Level Electromigration Accelerated Test (SWEAT). 63-68
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• José M. Quintana, Maria J. Avedillo, José Luis Huertas:
  Efficient Realization of a Threshold Voter for Self-Purging Redundancy. 69-73
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Volume 17, Number 2, April 2001

• Vishwani D. Agrawal:
  Editorial. 79
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• Marcelo Lubaszewski, Víctor H. Champac:
  Guest Editorial. 83-84
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• Antonio Zenteno, Víctor H. Champac, Joan Figueras:
  Detectability Conditions of Full Opens in the Interconnections. 85-95
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• Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian:
  An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. 97-107
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• P. Bukovjan, L. Ducerf-Bourbon, Meryem Marzouki:
  Cost/Quality Trade-off in Synthesis for BIST. 109-119
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• José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski:
  Fault Models and Test Generation for OpAmp Circuits - The FFM. 121-138
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• Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
  A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. 139-147
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• Érika F. Cota, Fernanda Lima, Sana Rezgui, Luigi Carro, Raoul Velazco, Marcelo Lubaszewski, Ricardo Reis:
  Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults. 149-161
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• Eduardo Augusto Bezerra, Fabian Vargas, Michael Paul Gough:
  Improving Reconfigurable Systems Reliability by Combining Periodical Test and Redundancy Techniques: A Case Study. 163-174
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• Silvia Regina Vergilio, José Carlos Maldonado, Mario Jino:
  Constraint Based Criteria: An Approach for Test Case Selection in the Structural Testing. 175-183
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• Alessandro Brawerman, Elias Procópio Duarte Jr.:
  An Isochronous Testing Strategy for Hierarchical Adaptive Distributed System-Level Diagnosis. 185-195
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Volume 17, Numbers 3-4, June 2001

• Vishwani D. Agrawal:
  Editorial. 203
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• Paolo Prinetto, Joan Figueras:
  Guest Editorial. 207
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• Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche:
  Test Challenges in Nanometer Technologies. 209-218
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• Anton Chichkov, Dirk Merlier, Peter Cox:
  Current Testing Procedure for Deep Submicron Devices. 219-224
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• Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev:
  Design for Delay Testability in High-Speed Digital ICs. 225-231
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• Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
  Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. 233-241
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• Daniela De Venuto, Michael J. Ohletz:
  On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages. 243-253
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• Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell:
  Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. 255-266
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• Antoni Ferré, Joan Figueras:
  LEAP: An Accurate Defect-Free I_DDQ Estimator. 267-274
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• Masaru Sanada:
  Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ. 275-281
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• Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
  A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. 283-290
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• Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik:
  Compressed Bit Fail Maps for Memory Fail Pattern Classification. 291-297
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• Nuno Cardoso, Carlos Beltrán Almeida, José Carlos Da Silva:
  A System Level Boundary Scan Controller Board for VME Applications. 299-310
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• Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
  RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. 311-319
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• Franco Fummi, Marco Boschini, Xiaoming Yu, Elizabeth M. Rudnick:
  Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach. 321-330
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• David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
  A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. 331-339
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• Sybille Hellebrand, Huaguo Liang, Hans-Joachim Wunderlich:
  A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. 341-349
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• Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich:
  Application of Deterministic Logic BIST on Industrial Circuits. 351-362
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Volume 17, Number 5, October 2001

• Vishwani D. Agrawal:
  Editorial. 367
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• André Ivanov:
  Test Technology Newsletter. 369-370
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• Michel Renovell:
  Guest Editorial. 371
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• Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
  New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. 373-383
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• Anna Maria Brosa, Joan Figueras:
  Digital Signature Proposal for Mixed-Signal Circuits. 385-393
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• Suresh Seshadri, Jacob A. Abraham:
  Frequency Response Verification of Analog Circuits Using Global Optimization Techniques. 395-408
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• Carsten Wegener, Michael Peter Kennedy, Bernd Straube:
  Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits. 409-416
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• Mustapha Slamani, Karim Arabi:
  Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques. 417-425
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• Hans G. Kerkhoff, Hans P. A. Hendriks:
  Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems. 427-437
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• Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet:
  Test and Testability of a Monolithic MEMS for Magnetic Field Sensing. 439-450
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Volume 17, Number 6, December 2001

• Vishwani D. Agrawal:
  Editorial. 455
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• Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois:
  Generation of Electrically Induced Stimuli for MEMS Self-Test. 459-470
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• Farzan Aminian, Mehran Aminian:
  Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks with Wavelet and Fourier Transforms as Preprocessors. 471-481
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• Jun-Weir Lin, Chung-Len Lee, Chau-chin Su, Jwu E. Chen:
  Fault Diagnosis for Linear Analog Circuits. 483-494
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• Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap:
  Fault Models and Test Procedures for Flash Memory Disturbances. 495-508
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• Mukul R. Prasad, Philip Chong, Kurt Keutzer:
  Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits? 509-527
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• Shivakumar Swaminathan, Krishnendu Chakrabarty:
  On Using Twisted-Ring Counters for Test Set Embedding in BIST. 529-542
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• Kanji Hirabayashi:
  An Algebraic Approach to Formal Verification of Microprocessors. 543-544
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