Journal of Electronic Testing, Volume 15

Volume 15, Numbers 1-2, August 1999

• Vishwani D. Agrawal:
  Editorial. 5
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• Michael Nicolaidis, Rob Roy:
  Guest Editorial. 9
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• Madhu K. Iyer, Michael L. Bushnell:
  Effect of Noise on Analog Circuit Testing. 11-22
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• R. de Vries, Augustus J. E. M. Janssen:
  Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling. 23-29
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• Ralph Mason, Shing Ma:
  Mixed Signal DFT at GHz Frequencies. 31-39
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• Fernando M. Gonçalves, João Paulo Teixeira:
  Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems. 41-52
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• Víctor H. Champac, José Castillejos, Joan Figueras:
  IDDQ Testing of Opens in CMOS SRAMs. 53-62
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• Ilker Hamzaoglu, Janak H. Patel:
  New Techniques for Deterministic Test Pattern Generation. 63-73
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• Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro:
  Efficient Path Selection for Delay Testing Based on Path Clustering. 75-85
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• Egor S. Sogomonyan, Adit D. Singh, Michael Gössel:
  A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. 87-96
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• Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray:
  Deterministic Built-in Pattern Generation for Sequential Circuits. 97-114
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• T. A. García, Antonio J. Acosta, J. M. Mora, J. Ramos, José Luis Huertas:
  Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. 115-127
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• Mehrdad Nourani, Christos A. Papachristou:
  Structural Fault Testing of Embedded Cores Using Pipelining. 129-144
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• Debaleena Das, Nur A. Touba:
  Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. 145-155
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• Jun Zhao, Fred J. Meyer, Fabrizio Lombardi:
  Adaptive Fault Detection and Diagnosis of RAM Interconnects. 157-171
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• Dinos Moundanos, Jacob A. Abraham:
  On Design Validation Using Verification Technology. 173-189
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• Li-C. Wang, Magdy S. Abadir:
  Experience in Validation of PowerPCTM Microprocessor Embedded Arrays. 191-205
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Volume 15, Number 3, December 1999

• Vishwani D. Agrawal:
  Editorial. 215
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• Bernd Becker, Martin Keim, Rolf Krieger:
  Hybrid Fault Simulation for Synchronous Sequential Circuits. 219-238
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• Michael S. Hsiao:
  On Non-Statistical Techniques for Fast Fault Coverage Estimation. 239-254
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• Chauchin Su, Shyh-Jye Jou:
  Decentralized BIST Methodology for System Level Interconnects. 255-265
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• Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis:
  An Accumulator-Based BIST Approach for Two-Pattern Testing. 267-278
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• Jacob Savir:
  Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections. 279-296
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• Jin Li, Xiaoling Sun:
  Tree-Structured Linear Cellular Automata and Their Applications in BIST. 297-300
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