Volume 22,
Number 1,
February 2006
- Vishwani D. Agrawal:
Editorial.
5
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- Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh:
New JETTA Editors, 2006.
9-10
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- Ali Chehab, Saurabh Patel, Rafic Z. Makki:
Scaling of iDDT Test Methods for Random Logic Circuits.
11-22
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- Audhild Vaaje:
Theorems for Fault Collapsing in Combinational Circuits.
23-36
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- Sunghoon Chun, Sangwook Kim, Hong-Sik Kim, Sungho Kang:
An Efficient Dictionary Organization for Maximum Diagnosis.
37-48
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- Zhen Shi, Peter Sandborn:
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly.
49-60
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- Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker:
Automatic Test Pattern Generation for Resistive Bridging Faults.
61-69
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- Hani Rizk, Christos A. Papachristou, Francis G. Wolff:
A Self Test Program Design Technique for Embedded DSP Cores.
71-87
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- Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Gated Clock Scheme for Low Power Testing of Logic Cores.
89-99
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- Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld:
Modulo p=3 Checking for a Carry Select Adder.
101-107
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Volume 22,
Number 2,
April 2006
- Vishwani D. Agrawal:
Editorial.
111
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- Bipul C. Paul, Kaushik Roy:
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.
115-124
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- Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.
125-142
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- Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin:
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m).
143-150
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- Yu-Chiun Lin, Shi-Yu Huang:
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults.
151-159
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- Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.
161-172
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- Zemo Yang, Samiha Mourad:
Crosstalk Induced Fault Analysis and Test in DRAMs.
173-187
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- Norbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet:
Electro-thermal Stimuli for MEMS Testing in FSBM Technology.
189-198
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- Fei Su, Sule Ozev, Krishnendu Chakrabarty:
Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems.
199-210
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Volume 22,
Number 3,
June 2006
- Jiun-Lang Huang, Jui-Jer Huang, Yuan-Shuang Liu:
A Low-Cost Jitter Measurement Technique for BIST Applications.
219-228
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- Jee-Youl Ryu, Bruce C. Kim, Iboun Taimiya Sylla:
A Novel RF Test Scheme Based on a DFT Method.
229-237
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- Jack Smith, Tian Xia, Charles E. Stroud:
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults.
239-253
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- Abhishek Singh, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel:
Defect Simulation Methodology for iDDT Testing.
255-272
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- Tao Lv, Jianping Fan, Xiaowei Li, Ling-Yi Liu:
Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification.
273-285
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- Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.
287-296
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- Markus Seuring:
Combining Scan Test and Built-in Self Test.
297-299
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- Franc Novak, Anton Biasizzo:
Security Extension for IEEE Std 1149.1.
301-303
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Volume 22,
Numbers 4-6,
December 2006
- Vishwani D. Agrawal:
Editorial.
307
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- Salvador Mir, Tim Cheng, Andrew Richardson:
Guest Editorial.
311
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- Carsten Wegener, Michael Peter Kennedy:
Test Development Through Defect and Test Escape Level Estimation for Data Converters.
313-324
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- Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro:
A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting.
325-335
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- Heinz Mattes, Stéphane Kirmser, Sebastian Sattler:
Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation.
337-350
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- Vincent Kerzerho, Serge Bernard, Philippe Cauvet, J. M. Janik:
A First Step for an INL Spectral-Based BIST: The Memory Optimization.
351-357
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- Kostas Georgopoulos, A. Lechner, M. Burbidge, Andrew Richardson:
Investigation into the Use of Hybrid Solutions for SigmaDelta A/D Converter Testing.
359-370
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- Tejasvi Das, Anand Gopalan, Clyde Washburn, P. R. Mukund:
Towards Fault-Tolerant RF Front Ends.
371-386
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- Jiun-Lang Huang:
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines.
387-398
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- Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud:
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits.
399-409
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- Yukiya Miura:
Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study.
411-423
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- Michel Morneau, Abdelhakim Khouas:
TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation.
425-436
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- Miguel Angel Domínguez, José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli:
A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing.
437-448
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- Amit Laknaur, Sai Raghuram Durbha, Haibo Wang:
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.
449-462
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- V. Loukusa:
Embedded System Level Self-Test for Mixed-Signal IO Verification.
463-470
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- Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee:
Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects.
471-482
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Copyright © Sat May 16 23:58:52 2009
by Michael Ley (ley@uni-trier.de)
