Journal of Electronic Testing, Volume 9

Volume 9, Numbers 1-2, August 1996

• Vishwani D. Agrawal:
  Editorial. 5
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• Bozena Kaminska, Bernard Courtois:
  Guest editorial. 7-8
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• J. van Spaandonk, Tom A. M. Kevenaar:
  Selecting measurements to test the functional behavior of analog circuits. 9-18
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• A. Gertners, V. Zagursky, D. Z. Saldava:
  Behavior model of mixed ADC systems. 19-27
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• Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
  A unified approach for fault simulation of linear mixed-signal circuits. 29-41
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• Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
  Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets. 43-57
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• Abdessatar Abderrahman, Bozena Kaminska, Eduard Cerny:
  Optimization-based multifrequency test generation for analog circuits. 59-73
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• José Machado da Silva, José Silva Matos, Ian M. Bell, Gaynor E. Taylor:
  Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits. 75-88
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• Javier Argüelles, Salvador Bracho:
  Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current. 89-107
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• Johan Verfaillie, Didier Haspeslagh:
  A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI. 109-115
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• Christian Dufaza, Hassan Ihs:
  A BIST-DFT technique for DC test of analog modules. 117-133
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• Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
  Unified built-in self-test for fully differential analog circuits. 135-151
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• Yingquan Zhou, Mike W. T. Wong, Yinghua Min:
  Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis. 153-163
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• J. Raczkowycz, S. Allott, T. I. Pritchard:
  A data optimization test technique for characterizing embedded ADCs. 165-175
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• Adel Belhaouane, Yvon Savaria, Bozena Kaminska, Daniel Massicotte:
  Reconstruction method for jitter tolerant data acquisition system. 177-185
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• Andrzej Materka, Michal Strzelecki:
  Parametric testing of mixed-signal circuits by ANN processing of transient responses. 187-202
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• Firas Mohamed, Meryem Marzouki:
  Test and diagnosis of analog circuits: When fuzziness can lead to accuracy. 203-216
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Volume 9, Number 3, December 1996

• Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta:
  Fault macromodeling and a testing strategy for opamps. 225-235
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• Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar:
  Initialization issues in asynchronous circuit synthesis. 237-250
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• Mark G. Karpovsky, Vyacheslav N. Yarmolik:
  Transparent random access memory testing for pattern sensitive faults. 251-266
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• Chen-Pin Kung, Chen-Shang Lin:
  Parallel sequence fault simulation for synchronous sequential circuits. 267-277
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• D. A. Pierce, Parag K. Lala:
  Modular implementation of efficient self-checking checkers for the Berger code. 279-294
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• Josep Rius, Joan Figueras:
  Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. 295-310
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• Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang:
  Cell delay fault testing for iterative logic arrays. 311-316
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