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| 2007 | ||
|---|---|---|
| 2 | EE | Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto: A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Transactions 90-C(10): 1927-1935 (2007) |
| 1996 | ||
| 1 | Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe: A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. ITC 1996: 319-324 | |
| 1 | Haruhiko Abe | [1] |
| 2 | Kazutami Arimoto | [2] |
| 3 | Katsumi Dosaka | [2] |
| 4 | Mitsuhiro Hamada | [1] |
| 5 | Shinji Komori | [1] |
| 6 | Kazuo Kyuma | [1] |
| 7 | Fukashi Morishita | [2] |
| 8 | Fumihiro Okuda | [1] |
| 9 | Narumi Sakashita | [1] |
| 10 | Ken'ichi Shimomura | [1] |
| 11 | Tetsuo Tada | [1] |
| 12 | Akihiko Yasuoka | [1] |