1996 |
14 | | Weiwei Mao,
Ravi K. Gulati:
Improving Gate Level Fault Coverage by RTL Fault Grading.
ITC 1996: 150-159 |
1994 |
13 | | Yunsheng Lu,
Weiwei Mao,
Ramaswami Dandapani,
Ravi K. Gulati:
Structure and Metrology for a Single-wire Analog.
ITC 1994: 919-928 |
12 | EE | Weiwei Mao,
Michael D. Ciletti:
Reducing correlation to improve coverage of delay faults in scan-path design.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 638-646 (1994) |
1992 |
11 | | Weiwei Mao,
Michael D. Ciletti:
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults.
ITC 1992: 588-597 |
10 | | Ravi K. Gulati,
Weiwei Mao,
Deepak K. Goel:
Detection of "Undetectable" Faults Using IDDQ Testing.
ITC 1992: 770-777 |
9 | EE | Jerry M. Soden,
Charles F. Hawkins,
Ravi K. Gulati,
Weiwei Mao:
IDDQ testing: A review.
J. Electronic Testing 3(4): 291-303 (1992) |
8 | EE | Weiwei Mao,
Ravi K. Gulati:
Quietest: A methodology for selecting IDDQ test vectors.
J. Electronic Testing 3(4): 349-357 (1992) |
1991 |
7 | EE | Weiwei Mao,
Michael D. Ciletti:
Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage.
DAC 1991: 73-79 |
1990 |
6 | EE | Weiwei Mao,
Michael D. Ciletti:
A Variable Observation Time Method for Testing Delay Faults.
DAC 1990: 728-731 |
5 | | Weiwei Mao,
Ravi K. Gulati,
Deepak K. Goel,
Michael D. Ciletti:
QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults.
ICCAD 1990: 280-283 |
4 | EE | Weiwei Mao,
Michael D. Ciletti:
DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 893-898 (1990) |
1989 |
3 | EE | Weiwei Mao,
Michael D. Ciletti:
A Simplified Six-waveform Type Method for Delay Fault Testing.
DAC 1989: 730-733 |
1988 |
2 | EE | Weiwei Mao,
Michael D. Ciletti:
Dytest: A Self-Learning Algorithm Using Dynamic Testability Measures to Accelerate Test Generation.
DAC 1988: 591-596 |
1986 |
1 | EE | Weiwei Mao,
Xieting Ling:
Robust test generation algorithm for stuck-open fault in CMOS circuits.
DAC 1986: 236-242 |