| |
| 1996 | ||
|---|---|---|
| 1 | Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe: A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. ITC 1996: 319-324 | |
| 1 | Mitsuhiro Hamada | [1] |
| 2 | Shinji Komori | [1] |
| 3 | Kazuo Kyuma | [1] |
| 4 | Fumihiro Okuda | [1] |
| 5 | Narumi Sakashita | [1] |
| 6 | Hiroki Shimano | [1] |
| 7 | Ken'ichi Shimomura | [1] |
| 8 | Tetsuo Tada | [1] |
| 9 | Akihiko Yasuoka | [1] |