| 1996 |
|---|
| 3 | | Narumi Sakashita,
Fumihiro Okuda,
Ken'ichi Shimomura,
Hiroki Shimano,
Mitsuhiro Hamada,
Tetsuo Tada,
Shinji Komori,
Kazuo Kyuma,
Akihiko Yasuoka,
Haruhiko Abe:
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.
ITC 1996: 319-324 |
| 1993 |
|---|
| 2 | | Eiichi Teraoka,
Toru Kengaku,
Ikuo Yasui,
Kazuyuki Ishikawa,
Takahiro Matsuo,
Hideyuki Wakada,
Narumi Sakashita,
Yukihiko Shimazu,
Takeshi Tokuda:
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC.
ITC 1993: 791-796 |
| 1988 |
|---|
| 1 | EE | Takeshi Tokuda,
Jiro Korematsu,
Yukihiko Shimazu,
Narumi Sakashita,
Tohru Kengaku,
Toshiki Fugiyama,
Takio Ohno,
Osamu Tomisawa:
A macrocell approach for VLSI processor design.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1272-1277 (1988) |
