Sandeep Bhatia

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11EENilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam: A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings. VLSI Design 2008: 187-193
10EESandeep Bhatia: Test Compaction by Using Linear-Matrix Driven Scan Chains. DFT 2003: 185-190
9EEPrab Varma, Sandeep Bhatia: A structured test re-use methodology for core-based system chips. ITC 1998: 294-302
8EESandeep Bhatia, Niraj K. Jha: Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. IEEE Trans. VLSI Syst. 6(4): 608-619 (1998)
7EESandeep Bhatia, Prab Varma: Test Compaction in a Parallel Access Scan Environment. Asian Test Symposium 1997: 300-305
6 Sandeep Bhatia, Tushar Gheewala, Prab Varma: A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC 1996: 639-648
5EESandeep Bhatia, Niraj K. Jha: Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 228-243 (1996)
4 Sandeep Bhatia, Niraj K. Jha: Genesis: A Behavioral Synthesis System for Hierarchical Testability. EDAC-ETC-EUROASIC 1994: 272-276
3 Sandeep Bhatia, Niraj K. Jha: Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. ICCD 1994: 91-96
2 Sandeep Bhatia, Niraj K. Jha: Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. ICCD 1993: 151-154
1 Sandeep Bhatia, Niraj K. Jha: Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. VLSI Design 1993: 275-280

Coauthor Index

1Nilabha Dev [11]
2Sue Genova [11]
3Tushar Gheewala [6]
4Niraj K. Jha [1] [2] [3] [4] [5] [8]
5Vinayak Kadam [11]
6Subhasish Mukherjee [11]
7Prab Varma [6] [7] [9]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)