2009 |
18 | EE | Bhanu Kapoor,
Shankar Hemmady,
Shireesh Verma,
Kaushik Roy,
Manuel A. d'Abreu:
Impact of SoC power management techniques on verification and testing.
ISQED 2009: 692-695 |
2008 |
17 | EE | Ramyanshu Datta,
Ravi Gupta,
Antony Sebastine,
Jacob A. Abraham,
Manuel A. d'Abreu:
Controllability of Static CMOS Circuits for Timing Characterization.
J. Electronic Testing 24(5): 481-496 (2008) |
2004 |
16 | EE | Ramyanshu Datta,
Ravi Gupta,
Antony Sebastine,
Jacob A. Abraham,
Manuel A. d'Abreu:
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.
ITC 2004: 1118-1127 |
2002 |
15 | EE | Manuel A. d'Abreu:
Noise-Its Sources, and Impact on Design and Test of Mixed Signal Circuits.
DELTA 2002: 370-376 |
2000 |
14 | EE | Manuel A. d'Abreu:
Manufacturing and Test Considerations in System-On-Chip Designs.
VLSI Design 2000: 176-177 |
1999 |
13 | | Rathish Jayabharathi,
Manuel A. d'Abreu,
Jacob A. Abraham:
FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model.
VLSI Design 1999: 232-235 |
1996 |
12 | EE | Prakash Arunachalam,
Jacob A. Abraham,
Manuel A. d'Abreu:
A Hierarchal Approach for Power Reduction in VLSI Chips.
Great Lakes Symposium on VLSI 1996: 182- |
11 | | Sankaran Karthik,
Mark Aitken,
Glidden Martin,
Srinivasu Pappula,
Bob Stettler,
Praveen Vishakantaiah,
Manuel A. d'Abreu,
Jacob A. Abraham:
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor.
ITC 1996: 160-166 |
1994 |
10 | EE | Jacob A. Abraham,
Sandip Kundu,
Janak H. Patel,
Manuel A. d'Abreu,
Bulent I. Dervisoglu,
Marc E. Levitt,
Hector R. Sucar,
Ron G. Walther:
Microprocessor Testing: Which Technique is Best? (Panel).
DAC 1994: 294 |
1993 |
9 | | Abhijit Chatterjee,
Rabindra K. Roy,
Manuel A. d'Abreu:
Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting.
VLSI Design 1993: 154-159 |
8 | | Abhijit Chatterjee,
Manuel A. d'Abreu:
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques.
IEEE Trans. Computers 42(7): 794-808 (1993) |
7 | EE | Abhijit Chatterjee,
Rabindra K. Roy,
Manuel A. d'Abreu:
Greedy hardware optimization for linear digital circuits using number splitting and refactorization.
IEEE Trans. VLSI Syst. 1(4): 423-431 (1993) |
1992 |
6 | EE | Rabindra K. Roy,
Abhijit Chatterjee,
Janak H. Patel,
Jacob A. Abraham,
Manuel A. d'Abreu:
Automatic test generation for linear digital systems with bi-level search using matrix transform methods.
ICCAD 1992: 224-228 |
1991 |
5 | | Abhijit Chatterjee,
Manuel A. d'Abreu:
Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems.
FTCS 1991: 136-143 |
4 | | Abhijit Chatterjee,
Manuel A. d'Abreu:
Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs.
ICCD 1991: 212-215 |
1989 |
3 | EE | William D. Smith,
David A. Duff,
M. Dragomirecky,
J. Caldwell,
Michael J. Hartman,
Jeffrey R. Jasica,
Manuel A. d'Abreu:
FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development.
DAC 1989: 466-471 |
2 | EE | M. Dragomirecky,
Ephraim P. Glinert,
Jeffrey R. Jasica,
David A. Duff,
William D. Smith,
Manuel A. d'Abreu:
High-Level Graphical User Interface Management in the FACE Synthesis Environment.
DAC 1989: 549-554 |
1988 |
1 | EE | E. Berkcan,
Manuel A. d'Abreu,
W. Laughton:
Analog Compilation Based on Successive Decompositions.
DAC 1988: 369-375 |