2006 |
6 | EE | Wilfried Haensch,
Edward J. Nowak,
Robert H. Dennard,
Paul M. Solomon,
Andres Bryant,
Omer H. Dokumaci,
Arvind Kumar,
Xinlin Wang,
Jeffrey B. Johnson,
Massimo V. Fischetti:
Silicon CMOS devices beyond scaling.
IBM Journal of Research and Development 50(4-5): 339-362 (2006) |
2002 |
5 | EE | Jack A. Mandelman,
Robert H. Dennard,
Gary B. Bronner,
John K. DeBrosse,
Rama Divakaruni,
Yujun Li,
Carl J. Raden:
Challenges and future directions for the scaling of dynamic random-access memory (DRAM).
IBM Journal of Research and Development 46(2-3): 187-222 (2002) |
2000 |
4 | EE | D. L. Critchlow,
Robert H. Dennard,
Stanley Schuster:
Design and characteristics of n-channel insulated-gate field-effect transistors.
IBM Journal of Research and Development 44(1): 70-83 (2000) |
1996 |
3 | | Thomas W. Williams,
Robert H. Dennard,
Rohit Kapur,
M. Ray Mercer,
Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling.
ITC 1996: 786-792 |
1995 |
2 | | G. G. Shahidi,
James D. Warnock,
James Comfort,
Stephen E. Fischer,
Patricia A. McFarland,
Alexandre Acovic,
Terry I. Chappell,
Barbara A. Chappell,
Tak H. Ning,
Carl J. Anderson,
Robert H. Dennard,
J. Y.-C. Sun,
Michael R. Polcari,
Bijan Davari:
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.
IBM Journal of Research and Development 39(1-2): 229-244 (1995) |
1 | | Alina Deutsch,
Gerard V. Kopcsay,
Christopher W. Surovic,
Barry J. Rubin,
Lewis M. Terman,
Richard P. Dunne Jr.,
Thomas A. Gallo,
Robert H. Dennard:
Modeling and characterization of long on-chip interconnections for high-performance microprocessors.
IBM Journal of Research and Development 39(5): 547-568 (1995) |