| 2000 |
|---|
| 9 | EE | Jawahar Jain,
K. Mohanram,
Dinos Moundanos,
Ingo Wegener,
Yuan Lu:
Analysis of composition complexity and how to obtain smaller canonical graphs.
DAC 2000: 681-686 |
| 1999 |
|---|
| 8 | EE | Dinos Moundanos,
Jacob A. Abraham:
Formal Checking of Properties in Complex Systems Using Abstractions.
Great Lakes Symposium on VLSI 1999: 280-283 |
| 7 | EE | Dinos Moundanos,
Jacob A. Abraham:
On Design Validation Using Verification Technology.
J. Electronic Testing 15(1-2): 173-189 (1999) |
| 1998 |
|---|
| 6 | EE | Dinos Moundanos,
Jacob A. Abraham:
Using Verification Technology for Validation Coverage Analysis and Test Generation.
VTS 1998: 254-259 |
| 5 | | Dinos Moundanos,
Jacob A. Abraham,
Yatin Vasant Hoskote:
Abstraction Techniques for Validation Coverage Analysis and Test Generation.
IEEE Trans. Computers 47(1): 2-14 (1998) |
| 1996 |
|---|
| 4 | EE | Prakash Arunachalam,
Craig M. Chase,
Dinos Moundanos:
Distributed Binary Decision Diagrams for Verification of Large Circuit.
ICCD 1996: 365-370 |
| 3 | | Dinos Moundanos,
Jacob A. Abraham,
Yatin Vasant Hoskote:
A Unified Framework for Design Validation and Manufacturing Test.
ITC 1996: 875-884 |
| 1995 |
|---|
| 2 | EE | Yatin Vasant Hoskote,
Dinos Moundanos,
Jacob A. Abraham:
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors.
ICCD 1995: 532-537 |
| 1 | EE | Jawahar Jain,
Dinos Moundanos,
James R. Bitner,
Jacob A. Abraham,
Donald S. Fussell,
Don E. Ross:
Efficient variable ordering and partial representation algorithm.
VLSI Design 1995: 81-86 |
