EDAC 1994:
Paris,
France
Robert Werner (Ed.):
EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France.
IEEE Computer Society 1994, ISBN 0-8186-5410-4 BibTeX
Session 1A:
Processor Architecture
- George Alexiou, Dimitrios Stiliadis, Nick Kanopoulos:
Design and Implementation of a High-Performance, Modular, Sorting Engine.
2-8 BibTeX
- Alain Greiner, L. Lucas, Franck Wajsbürt, Laurent Winckel:
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library.
9-13 BibTeX
- T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier:
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads.
14-18 BibTeX
Session 1B:
System Level Transformation and Micro Code Generation
Session 1C:
Testing Sequential Circuits.
Session 2A:
System Design and Mixed A/D Synthesis
- Huy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet:
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System.
60-64 BibTeX
- Fermín Calvo, Pierre Plaza, Pedro Mateos:
ICM2 IC: a new ATM switching element for 2.48 Gb/s communications.
65-69 BibTeX
- R. van Dongen, V. Rikkink:
Advanced Analog Circuit Design on a Digital Sea-of-Gates Array.
70-74 BibTeX
- Dorine Gevaert, Jozef Vanneuville, Jiri Nedved, Jan Sevenhans:
Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End.
75-79 BibTeX
Session 2B:
Circuit Optimization and Partitioning
Session 2C:
BIST Techniques
Session 3A:
Finite State Machine Verification
Session 3C:
Fault Modeling
Session 4A:
Synchronous Finite State Machines
Session 4B:
New BDD-Concepts
Session 4C:
Applications of Boundary Scan
Session 5A:
DSP Implementations
Session 5B:
Algorithmic Transformations in High-Level Synthesis
Session 5C:
DFT for Delay Faults and Sequential Machines
Session 6A:
Estimation During High-Level Synthesis
Session 6B:
Towards Statistical and High-Level Timing Analysis
Session 6C:
Bridging Faults in Testing
Session 7A:
Specification and Synthesis of System Interfaces
Session 7C:
Routing
Session 8A:
Performance Issues in Physical Design
Session 8C:
Various Views on Testing Efficiency
Session 9A:
Design Methodologies for the System-Level
Session 9B:
Applications of Scheduling in High-Level Synthesis
- Bruno Rouzeyre, D. Dupont, G. Sagnes:
Component Selection, Scheduling and Control Schemes for High Level Synthesis.
482-489 BibTeX
- Francis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man:
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization.
490-494 BibTeX
- Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani:
Scheduling with Environmental Constraints based on Automata Representations.
495-501 BibTeX
- Koen Schoofs, Gert Goossens, Hugo De Man:
Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures.
502-506 BibTeX
Session 9C:
Delay Test
Session 10A:
Tools and Methods for Analogue System Design
- Stéphane Donnay, Koen Swings, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts:
A Methodology for Analog Design Automation in Mixed-Signal ASICs.
530-534 BibTeX
- Vincent Moser, Pascal Nussbaum, Hans Peter Amann, Luc Astier, Fausto Pellandini:
A Graphical Approach to Analogue Behavioural Modelling.
535-539 BibTeX
- Eamonn Byrne, Oliver McCarthy, David Lucas, Brian Donnellan:
An Overview of Analogue Optimisation Using "AD-OPT".
540-545 BibTeX
- Makoto Ikeda, Kunihiro Asada:
A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs.
546-550 BibTeX
Session 10B:
Logic,
Circuit,
and Yield Simulation Technologies
Session 10C:
DFT for Datapaths,
Controllers,
and Arrays
Session 11A:
Framework Services for Productivity Improvement
- M. Straube, Wolfgang Wilkes, Gunter Schlageter:
HANDICAP - A System for Design Consulting.
600-604 BibTeX
- Gunnar Bartels, Peter Kist, Kees Schot, Mattie Sim:
Flow Management Requirements of a Test Harness for Testing the Reliability of an Electronic CAD System.
605-609 BibTeX
- Sandip Parikh, David Sarnoff, Michael L. Bushnell, James Sienicki, Ramakrishnan Ganesh:
Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework.
610-617 BibTeX
Session 11B:
Techniques and Applications for BDDs
Session 11C:
High-Level Verification
Poster Session
- N. M. Vitsyn:
The Russian EDA Standards Activities.
654 BibTeX
- Thomas Johansson, L. R. Virtanen, J. M. Gobbi:
``Underground Capacitors'' Very Efficient Decoupling for High Performance UHF Signal Processing ICs.
655 BibTeX
- Michel Robert, P. Gorria, Johel Mitéran, S. Turgis:
Design of a Real Time Geometric Classifier.
656 BibTeX
- Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto:
From Behavioral Description to Systolic Array Based Architectures.
657 BibTeX
- Abdessatar Abderrahman, Bozena Kaminska, Yvon Savaria:
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits.
658 BibTeX
- H. H. Ahmad, R. J. Mack:
AREAL: Automated Reasoning Expert for Analogue Layout.
659 BibTeX
- Jean-Claude Dufourd, Jean-François Naviner:
An Optimizable Model for Process Independent Symbolic Design.
660 BibTeX
- Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin:
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning.
661 BibTeX
- Wolfgang Vermeiren, Bernd Straube, Günter Elst:
A Suggestion for Accelerating the Analog Fault Simulation.
662 BibTeX
- K. C. Koudakou:
Software Implementation and Statistical Optimization of Some Electronic Component's Lifetime.
663 BibTeX
- Andrea Boni, G. Chiorboli, G. Franco, S. Mazzoleni, M. Ostacoli:
Physical Modeling of Linearity Errors for the Diagnosis of High Resolution R-2R D/A Converters.
664 BibTeX
- Salman Ahmed, Peter Y. K. Cheung, Phil Collins:
A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation.
665 BibTeX
- A. J. van de Goor, Yervant Zorian, Ivo Schanstra:
Functional Tests for Ring-Address SRAM-type FIFOs.
666 BibTeX
- Bernd Becker, Rolf Drechsler:
Testability of Circuits Derived from Functional Decision Diagrams.
667 BibTeX
- M. Hirech, O. Florent, Alain Greiner, E. Rejouan:
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking.
668 BibTeX
- Luc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary:
Multilevel Logic Synthesis of Very High Complexity Circuits.
669 BibTeX
- Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan:
Signal Transition Graph Transformations for Initializability.
670 BibTeX
- Muhammad K. Dhodhi, Imtiaz Ahmad, C. Y. Roger Chen:
Synthesis of Application-Specific Multiprocessor Systems.
671 BibTeX
- Peter Zepter, Thorsten Grötker:
Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations.
672 BibTeX
Copyright © Sat May 16 23:11:12 2009
by Michael Ley (ley@uni-trier.de)
