| 2000 |
|---|
| 8 | EE | Daniel Gajski,
Allen C.-H. Wu,
Viraphol Chaiyakul,
Shojiro Mori,
Tom Nukiyama,
Pierre Bricaud:
Embedded tutorial: essential issues for IP reuse.
ASP-DAC 2000: 37-42 |
| 7 | EE | Nong Fan,
Viraphol Chaiyakul,
Daniel Gajski:
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis.
ASP-DAC 2000: 43-48 |
| 1996 |
|---|
| 6 | EE | Hsiao-Ping Juan,
Daniel Gajski,
Viraphol Chaiyakul:
Clock-driven performance optimization in interactive behavioral synthesis.
ICCAD 1996: 154-157 |
| 1994 |
|---|
| 5 | | Loganath Ramachandran,
Daniel Gajski,
Viraphol Chaiyakul:
An Algorithm for Array Variable Clustering.
EDAC-ETC-EUROASIC 1994: 262-266 |
| 4 | EE | Hsiao-Ping Juan,
Viraphol Chaiyakul,
Daniel D. Gajski:
Condition graphs for high-quality behavioral synthesis.
ICCAD 1994: 170-174 |
| 1993 |
|---|
| 3 | EE | Viraphol Chaiyakul,
Daniel Gajski,
Loganath Ramachandran:
High-Level Transformations for Minimizing Syntactic Variances.
DAC 1993: 413-418 |
| 1992 |
|---|
| 2 | EE | Champaka Ramachandran,
Fadi J. Kurdahi,
Daniel Gajski,
Allen C.-H. Wu,
Viraphol Chaiyakul:
Accurate layout area and delay modeling for system level design.
ICCAD 1992: 355-361 |
| 1991 |
|---|
| 1 | | Allen C.-H. Wu,
Viraphol Chaiyakul,
Daniel Gajski:
Layout-Area Models for High-Level Synthesis.
ICCAD 1991: 34-37 |
