M. Hirech

2008
3	EE	C. P. Ravikumar, M. Hirech, X. Wen: Test Strategies for Low Power Devices. DATE 2008: 728-733
1994
2		M. Hirech, O. Florent, Alain Greiner, E. Rejouan: A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. EDAC-ETC-EUROASIC 1994: 668
1		M. Hirech, O. Florent, Alain Greiner, E. Rejouan: A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. ISCAS 1994: 89-92

Coauthor Index

1	O. Florent	[1] [2]
2	Alain Greiner	[1] [2]
3	C. P. Ravikumar	[3]
4	E. Rejouan	[1] [2]
5	X. Wen	[3]

Colors in the list of coauthors