| 2008 |
|---|
| 43 | EE | Chen-Yuan Chu,
Chien-Cheng Wei,
Hui-Chen Hsu,
Shu-Hau Feng,
Wu-Shiung Feng:
A 24GHz low-power CMOS receiver design.
ISCAS 2008: 980-983 |
| 42 | EE | Chia-Chi Chu,
Ming-Hong Lai,
Wu-Shiung Feng:
Model-order reductions for MIMO systems using global Krylov subspace methods.
Mathematics and Computers in Simulation 79(4): 1153-1164 (2008) |
| 2007 |
|---|
| 41 | EE | Ming-Hong Lai,
Chia-Chi Chu,
Wu-Shiung Feng:
Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis.
ISCAS 2007: 1133-1136 |
| 40 | EE | Ming-Hong Lai,
Chia-Chi Chu,
Wu-Shiung Feng:
On the Equivalent of Structure Preserving Reductions Approach and Adjoint Networks Approach for VLSI Interconnect Reductions.
IEICE Transactions 90-A(2): 411-414 (2007) |
| 39 | EE | Chia-Chi Chu,
Ming-Hong Lai,
Wu-Shiung Feng:
Lyapunov-Based Error Estimations of MIMO Interconnect Reductions by Using the Global Arnoldi Algorithm.
IEICE Transactions 90-A(2): 415-418 (2007) |
| 2006 |
|---|
| 38 | EE | Ming-Hong Lai,
Chia-Chi Chu,
Wu-Shiung Feng:
The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reductions.
APCCAS 2006: 1268-1271 |
| 37 | EE | Ming-Hong Lai,
Chia-Chi Chu,
Wu-Shiung Feng:
Model-Order Reduction Algorithm with Structure Preserving Techniques.
APCCAS 2006: 1607-1610 |
| 36 | EE | Ming-Hong Lai,
Chia-Chi Chu,
Wu-Shiung Feng:
MIMO interconnects order reductions by using the global Arnoldi algorithm.
ISCAS 2006 |
| 35 | EE | Chia-Chi Chu,
Ming-Hong Lai,
Wu-Shiung Feng:
The global Lanczos method for MIMO interconnect order reductions.
ISCAS 2006 |
| 34 | EE | Chia-Chi Chu,
Ming-Hong Lai,
Wu-Shiung Feng:
The Multiple Point Global Lanczos Method for Multiple-Inputs Multiple-Outputs Interconnect Order Reductions.
IEICE Transactions 89-A(10): 2706-2716 (2006) |
| 33 | EE | Chia-Chi Chu,
Herng-Jer Lee,
Ming-Hong Lai,
Wu-Shiung Feng:
An Adjoint Network Approach for RLCG Interconnect Model Order Reductions.
IEICE Transactions 89-A(2): 439-447 (2006) |
| 32 | EE | Chia-Chi Chu,
Ming-Hong Lai,
Wu-Shiung Feng:
MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm.
IEICE Transactions 89-C(6): 792-802 (2006) |
| 31 | EE | Ying-Haw Shu,
Shing Tenqchen,
Ming-Chang Sun,
Wu-Shiung Feng:
A Brief Comparison of Two-phase and NOR-based Four-phase Pipelined Asynchronous Systems.
J. Inf. Sci. Eng. 22(4): 941-952 (2006) |
| 2005 |
|---|
| 30 | EE | Hwang-Cherng Chow,
Bo-Wei Chen,
Hsiao-Chen Chen,
Wu-Shiung Feng:
A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications.
ISCAS (1) 2005: 736-739 |
| 29 | EE | Chia-Chi Chu,
Herng-Jer Lee,
Wu-Shiung Feng,
Ming-Hong Lai:
Interconnect model reductions by using the AORA algorithm with considering the adjoint network.
ISCAS (2) 2005: 1278-1281 |
| 28 | EE | Chia-Chi Chu,
Ming-Hong Lai,
Wu-Shiung Feng:
Perturbation Approach for Order Selections of Two-Sided Oblique Projection-Based Interconnect Reductions.
IEICE Transactions 88-A(12): 3573-3576 (2005) |
| 27 | EE | Chia-Chi Chu,
Herng-Jer Lee,
Wu-Shiung Feng:
Error Estimations of Arnoldi-Based Interconnect Model-Order Reductions.
IEICE Transactions 88-A(2): 533-537 (2005) |
| 26 | EE | Ming-Chang Sun,
Ying-Haw Shu,
Shing Tenqchen,
Wu-Shiung Feng:
A One-Step Input Matching Method for Cascode CMOS Low-Noise Amplifiers.
IEICE Transactions 88-C(3): 420-428 (2005) |
| 25 | EE | Herng-Jer Lee,
Chia-Chi Chu,
Ming-Hong Lai,
Wu-Shiung Feng:
Moment Computations of Distributed Coupled RLC Interconnects with Applications to Estimating Crosstalk Noise.
IEICE Transactions 88-C(6): 1186-1195 (2005) |
| 2004 |
|---|
| 24 | EE | Shing Tenqchen,
Ying-Haw Shu,
Ming-Chang Sun,
Wu-Shiung Feng:
Blind Signal Extraction Algorithm for the License Plate Matching of Vehicle Positioning System.
DELTA 2004: 440-442 |
| 23 | | Herng-Jer Lee,
Chia-Chi Chu,
Wu-Shiung Feng:
Generalizations of adjoint networks technique for RLC interconnects model-order reductions.
ISCAS (1) 2004: 185-188 |
| 22 | EE | Herng-Jer Lee,
Ming-Hong Lai,
Chia-Chi Chu,
Wu-Shiung Feng:
Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops.
ISCAS (1) 2004: 713-716 |
| 21 | EE | Herng-Jer Lee,
Chia-Chi Chu,
Wu-Shiung Feng:
Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise.
ISQED 2004: 75-80 |
| 2003 |
|---|
| 20 | EE | Ming-Chang Sun,
Shing Tenqchen,
Ying-Haw Shu,
Wu-Shiung Feng:
A 2.4 GHz CMOS image-reject low noise amplifier.
ISCAS (1) 2003: 329-332 |
| 19 | EE | Herng-Jer Lee,
Chia-Chi Chu,
Wu-Shiung Feng:
Interconnect modeling and sensitivity analysis using adjoint networks reduction technique.
ISCAS (4) 2003: 648-651 |
| 2002 |
|---|
| 18 | EE | Herng-Jer Lee,
Chia-Chi Chu,
Wu-Shiung Feng:
Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models.
APCCAS (1) 2002: 257-262 |
| 17 | EE | Chin Hsia,
Ming-Hong Lai,
Wu-Shiung Feng:
On-board effective inductance measurement.
APCCAS (1) 2002: 443-446 |
| 16 | EE | Shing Tenqchen,
Ji-Horn Chang,
Wu-Shiung Feng,
Bor-Sheng Jeng:
Pipelining Extended Givens Rotation RLS Adaptive Filters.
DELTA 2002: 466-473 |
| 15 | EE | Herng-Jer Lee,
Chia-Chi Chu,
Wu-Shiung Feng:
Intelligent multipoint Arnoldi (IMA) approximations of FIR filters by low-order linear-phase IIR filters.
ISCAS (1) 2002: 417-420 |
| 2001 |
|---|
| 14 | EE | Chih-Chun Tang,
Wen-Shih Lu,
Lan-Da Van,
Wu-Shiung Feng:
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage.
ISCAS (4) 2001: 794-797 |
| 1999 |
|---|
| 13 | EE | Lan-Da Van,
Shuenn-Shyang Wang,
Shing Tenqchen,
Wu-Shiung Feng,
Bor-Shenn Jeng:
Design of a lower-error fixed-width multiplier for speech processing application.
ISCAS (3) 1999: 130-133 |
| 1995 |
|---|
| 12 | EE | Chun-Jung Chen,
Wu-Shiung Feng:
Relaxation-based transient sensitivity computations for MOSFET circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 173-185 (1995) |
| 1994 |
|---|
| 11 | EE | Chung-Jung Chen,
Wu-Shiung Feng:
Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation.
DAC 1994: 581-585 |
| 10 | | Jyh-Herng Wang,
Jen-Teng Fan,
Wu-Shiung Feng:
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits.
EDAC-ETC-EUROASIC 1994: 562-566 |
| 1992 |
|---|
| 9 | EE | Sung-Chuan Fang,
Wu-Shiung Feng,
Shian-Lang Lee:
A New Efficient Approach to Multilayer Channel Routing Problem.
DAC 1992: 579-584 |
| 8 | EE | Chia-Chun Tsai,
Sao-Jie Chen,
Wu-Shiung Feng:
An H-V alternating router.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 976-991 (1992) |
| 1991 |
|---|
| 7 | EE | Sung-Chuan Fang,
Kuo-En Chang,
Wu-Shiung Feng,
Sao-Jie Chen:
Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems.
DAC 1991: 60-65 |
| 6 | | Chun-Jung Chen,
Jyuo-Min Shyu,
Wu-Shiung Feng:
Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation.
ICCAD 1991: 120-123 |
| 5 | EE | Pei-Yung Hsiao,
S. F. Steven Chen,
Chia-Chun Tsai,
Wu-Shiung Feng:
A knowledge-based program for compacting mask layout of integrated circuits.
Computer-Aided Design 23(3): 223-231 (1991) |
| 1990 |
|---|
| 4 | EE | Chia-Chun Tsai,
Sao-Jie Chen,
Wu-Shiung Feng:
Generalized terminal connectivity problem for multilayer layout scheme.
Computer-Aided Design 22(7): 423-433 (1990) |
| 3 | EE | Pei-Yung Hsiao,
Wu-Shiung Feng:
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(5): 522-536 (1990) |
| 2 | EE | Chia-Chun Tsai,
Sao-Jie Chen,
Wu-Shiung Feng:
An H-V Tile-Expansion Router.
J. Inf. Sci. Eng. 6(3): 173-189 (1990) |
| 1989 |
|---|
| 1 | | S. F. Steven Chen,
Pei-Yung Hsiao,
Wu-Shiung Feng,
Shun-Nan Dai,
Wen-Zyh Wang:
The Control Model for a Knowledge-Based Approach to VLSI Compaction Design.
IFIP Congress 1989: 241-246 |
