| 1996 |
|---|
| 6 | EE | Chennian Di,
Jochen A. G. Jess:
An efficient CMOS bridging fault simulator: with SPICE accuracy.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1071-1080 (1996) |
| 1994 |
|---|
| 5 | | Hua Xue,
Chennian Di,
Jochen A. G. Jess:
Probability Analysis for CMOS Floating Gate Faults.
EDAC-ETC-EUROASIC 1994: 443-448 |
| 1993 |
|---|
| 4 | | Hua Xue,
Chennian Di,
Jochen A. G. Jess:
Fast Multi-Layer Critical Area Computation.
DFT 1993: 117-124 |
| 3 | EE | Hua Xue,
Chennian Di,
Jochen A. G. Jess:
A net-oriented method for realistic fault analysis.
ICCAD 1993: 78-83 |
| 2 | | Chennian Di,
Jochen A. G. Jess:
On Accurate Modeling and Efficient Simulation of CMOS Opens.
ITC 1993: 875-882 |
| 1992 |
|---|
| 1 | EE | José Pineda de Gyvez,
Chennian Di:
IC defect sensitivity for footprint-type spot defects.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 638-658 (1992) |
