| 2000 |
|---|
| 8 | EE | Mitrajit Chatterjee,
Savita Banerjee,
Dhiraj K. Pradhan:
Buffer Assignment Algorithms on Data Driven ASICs.
IEEE Trans. Computers 49(1): 16-32 (2000) |
| 1996 |
|---|
| 7 | EE | Savita Banerjee,
Srimat T. Chakradhar,
Rabindra K. Roy:
Synchronous Test Generation Model for Asynchronous Circuits.
VLSI Design 1996: 178-185 |
| 6 | EE | Srimat T. Chakradhar,
Savita Banerjee,
Rabindra K. Roy,
Dhiraj K. Pradhan:
Synthesis of initializable asynchronous circuits.
IEEE Trans. VLSI Syst. 4(2): 254-263 (1996) |
| 5 | EE | Savita Banerjee,
Rabindra K. Roy,
Srimat T. Chakradhar:
Initialization issues in asynchronous circuit synthesis.
J. Electronic Testing 9(3): 237-250 (1996) |
| 1994 |
|---|
| 4 | | Savita Banerjee,
Rabindra K. Roy,
Srimat T. Chakradhar,
Dhiraj K. Pradhan:
Signal Transition Graph Transformations for Initializability.
EDAC-ETC-EUROASIC 1994: 670 |
| 3 | | Savita Banerjee,
Rabindra K. Roy,
Srimat T. Chakradhar,
Dhiraj K. Pradhan:
Initialization Isuues in the Synthesis of Asynchronous Circuits.
ICCD 1994: 447-452 |
| 2 | | Srimat T. Chakradhar,
Savita Banerjee,
Rabindra K. Roy,
Dhiraj K. Pradhan:
Synthesis of Initializable Asynchronous Circuits.
VLSI Design 1994: 383-388 |
| 1993 |
|---|
| 1 | EE | Dhiraj K. Pradhan,
Mitrajit Chatterjee,
Savita Banerjee:
Buffer assignment for data driven architectures.
ICCAD 1993: 665-668 |
