How-Rern Lin

List of publications from the DBLP Bibliography Server - FAQ

1999

4 EE How-Rern Lin, TingTing Hwang: On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 231-238 (1999)

1995

3 EE How-Rern Lin, TingTing Hwang: Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC 1995

1994

2 How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang: Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429

1 EE How-Rern Lin, TingTing Hwang: Dynamical identification of critical paths for iterative gate sizing. ICCAD 1994: 481-484

1999
4	EE	How-Rern Lin, TingTing Hwang: On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 231-238 (1999)
1995
3	EE	How-Rern Lin, TingTing Hwang: Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC 1995
1994
2		How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang: Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429
1	EE	How-Rern Lin, TingTing Hwang: Dynamical identification of critical paths for iterative gate sizing. ICCAD 1994: 481-484

Coauthor Index